EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 362

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–82
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 3 of 3)
Cyclone IV Device Handbook, Volume 2
RX PCS
RX PMA
Block
rx_coreclk
rx_phase_comp_
fifo_error
rx_bitslipboun
daryselectout
rx_datain
rx_freqlocked
rx_locktodata
rx_locktoref
clk
rx_signalde
tect
rx_recovclkout
Port Name
Output
Output Clock signal
Output
Output Asynchronous signal.
Output Asynchronous signal
Output Asynchronous signal
Output Asynchronous signal
Output Asynchronous signal
Output Clock signal
Input/
Input
Synchronous to tx_clkout (non-
bonded modes) or coreclkout
(bonded modes)
N/A
Clock Domain
Chapter 1: Cyclone IV Transceivers Architecture
Optional read clock port for the RX phase compensation
FIFO.
RX phase compensation FIFO full or empty indicator.
■
Indicate the number of bits slipped in the word aligner
configured in manual alignment mode.
■
Receiver serial data input port.
Receiver CDR lock state indicator
■
■
Receiver CDR LTD state control signal
■
■
Receiver CDR LTR state control signal.
■
Signal threshold detect indicator.
■
■
CDR low-speed recovered clock
■
A high level indicates FIFO is either full or empty.
Values range from 0 to 9.
A high level indicates the CDR is in LTD state.
A low level indicates the CDR is in LTR state.
A high level forces the CDR to LTD state
When deasserted, the receiver CDR lock state depends
on the rx_locktorefclk signal level.
The rx_locktorefclk and rx_locktodata
signals control whether the receiver CDR states as
follows:
[rx_locktodata:rx_locktorefclk]



Available in Basic mode when 8B/10B encoder/decoder
is used, and in PIPE mode.
A high level indicates that the signal present at the
receiver input buffer is above the programmed signal
detection threshold value.
Only available in the GIGE mode for applications such as
Synchronous Ethernet.
2'b00—receiver CDR is in automatic lock mode
2b'01—receiver CDR is in manual lock mode (LTR
state)
2b'1x—receiver CDR is in manual lock mode (LTD
state)
© December 2010 Altera Corporation
Transceiver Top-Level Port Lists
Description