EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 320

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–40
Table 1–13. Automatic RX Phase Compensation FIFO Read Clock Selection
Cyclone IV Device Handbook, Volume 2
Non-bonded
Bonded
Note to
(1) Configuration with rate match FIFO is supported in transmitter and receiver operation.
Table 1–13
Channel Configuration
1
:
With rate match FIFO
(1)
Without rate match
FIFO
With rate match FIFO
(1)
Without rate match
FIFO
In the receiver datapath, RX phase compensation FIFO forms the receiver-FPGA
fabric interface. Data and status signals from the receiver are clocked with the FIFO
read clock. The FIFO read clock supports automatic clock selection by the Quartus II
software (depending on channel configuration), or user-specified clock from
rx_coreclk port.
read clock selection by the Quartus II software.
The Quartus II software assumes automatic clock selection for RX phase
compensation FIFO read clock if you do not enable the rx_coreclk port.
When using user-specified clock option, ensure that the clock feeding rx_coreclk
port has 0 PPM difference with the RX phase compensation FIFO write clock.
tx_clkout clock feeds the FIFO read clock. tx_clkout is forwarded
through the receiver channel from low-speed clock, which also feeds the FIFO
write clock and transmitter PCS.
rx_clkout clock feeds the FIFO read clock. rx_clkout is forwarded
through the receiver channel from low-speed recovered clock, which also feeds
the FIFO write clock.
coreclkout clock feeds the FIFO read clock for the bonded channels.
coreclkout clock is the common bonded low-speed clock, which also feeds
the FIFO read clock and transmitter PCS in the bonded channels.
rx_clkout clock feeds the FIFO read clock. rx_clkout is forwarded
through the receiver channel from low-speed recovered clock, which also feeds
the FIFO write clock.
Table 1–13
details the automatic RX phase compensation FIFO
Quartus II Selection
Chapter 1: Cyclone IV Transceivers Architecture
© December 2010 Altera Corporation
Transceiver Clocking Architecture