EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 293

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
Clock Data Recovery
© December 2010 Altera Corporation
Each receiver channel has an independent CDR unit to recover the clock from the
incoming serial data stream. The high-speed recovered clock is used to clock the
deserializer for serial-to-parallel conversion of the received input data, and low-speed
recovered clock to clock the receiver PCS blocks.
block diagram.
Figure 1–15. CDR Unit Block Diagram
Notes to
(1) EP4CGX30 (F484 package), EP4CGX50, and EP4CGX75 devices support optional wider spread of asynchronous
(2) Optional RX local divider for CDR clocks from multipurpose PLL is only available in each CDR unit for EP4CGX30
(3) CDR state transition in automatic lock mode is not dependent on rx_signaldetect signal, except when
Each CDR unit gets the reference clock from one of the two multipurpose
phase-locked loops (PLLs) adjacent to the transceiver block. The CDR works by
tracking the incoming data with a phase detector and finding the optimum sampling
clock phase from the phase interpolator unit. The CDR operations are controlled by
the LTR/LTD controller block, where the CDR may operate in the following states:
■
■
State transitions are supported with automatic lock mode and manual lock mode.
Automatic Lock Mode
Upon receiver power-up and reset cycle, the CDR is put into LTR state. Transition to
the LTD state is performed automatically when both of the following conditions are
met:
■
rx_signaldetect(3)
Lock-to-reference (LTR) state—phase detector disabled and CDR ignores incoming
data
Lock-to-data (LTD) state—phase detector enabled and CDR tracks incoming data
to find the optimum sampling clock phase
Signal detection circuitry indicates the presence of valid signal levels at the
receiver input buffer. This condition is valid for PCI Express (PIPE) mode only.
CDR transitions are not dependent on signal detection circuitry in other modes.
spread-spectrum clocking (SSC) with triangular frequency modulation profile only. For the supported SSC spread
range, refer to the
(F484 package), EP4CGX50, and EP4CGX75 devices. This block is used with the transceiver dynamic reconfiguration
feature. For more information, refer to the
Dynamic Reconfiguration in Cyclone IV GX
configured in PCI Express (PIPE) mode only.
rx_locktorefclk
rx_locktodata
rx_freqlocked
CDR clocks
Figure
from MPLL
rx_datain
1–15:
Cyclone IV Device Data
Controller
LTR/LTD
/2
(2)
Interpolator
Sheet.
Cyclone IV Dynamic Reconfiguration
Detector
(Note 1)
Devices.
Phase
Phase
Sampling
Clocks
Up
Down
Figure 1–15
Divider
Clock
Cyclone IV Device Handbook, Volume 2
chapter and
illustrates the CDR unit
High-speed recovered
clock (for deserializer)
Low-speed recovered
clock (for receiver PCS)
AN 609: Implementing
1–13