EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 84

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–22
Clock Feedback Modes
Source-Synchronous Mode
Cyclone IV Device Handbook, Volume 1
1
1
Cyclone IV PLLs support up to five different clock feedback modes. Each mode
allows clock multiplication and division, phase shifting, and programmable duty
cycle. For the supported feedback modes, refer to
Cyclone IV GX PLLs and
Input and output delays are fully compensated by the PLL only if you are using the
dedicated clock input pins associated with a given PLL as the clock sources.
When driving the PLL using the GCLK network, the input and output delays may not
be fully compensated in the Quartus II software.
If the data and clock arrive at the same time at the input pins, the phase relationship
between the data and clock remains the same at the data and clock ports of any I/O
element input register.
Figure 5–12
mode for source-synchronous data transfers. Data and clock signals at the I/O
element experience similar buffer delays as long as the same I/O standard is used.
Figure 5–12. Phase Relationship Between Data and Clock in Source
Source-synchronous mode compensates for delay of the clock network used,
including any difference in the delay between the following two paths:
■
■
Set the input pin to the register delay chain in the I/O element to zero in the
Quartus II software for all data pins clocked by a source-synchronous mode PLL.
Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II
software.
Data pin to I/O element register input
Clock input pin to the PLL phase frequency detector (PFD) input
shows an example waveform of the data and clock in this mode. Use this
clock at input pin
Clock at register
Data at register
PLL reference
Table 5–6 on page 5–18
Data pin
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
for Cyclone IV E PLLs.
Table 5–5 on page 5–17
© December 2010 Altera Corporation
- Synchronous Mode
Clock Feedback Modes
for