EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 345

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Table 1–21. XGMII Character to PCS Code Groups Mapping (Part 2 of 2)
Table 1–22. PCS Code Groups to XGMII Character Mapping
© December 2010 Altera Corporation
Notes to
(1) Equivalent to tx_ctrlenable port.
(2) Equivalent to 8-bit input data to 8B/10B encoder.
(3) The values in XGMII TXD column are in hexadecimal.
Notes to
(1) Equivalent to rx_ctrlenable port.
(2) Equivalent to 8-bit input data to 8B/10B encoder.
(3) The values in XGMII RXD column are in hexadecimal.
XGMII RXC
XGMII TXC
0
1
1
1
1
1
1
1
1
Table
Table
(1)
(1)
1–21:
1–22:
XGMII RXD (2),
XGMII TXD (2),
8B/10B decoder in the receiver datapath maps received PCS code groups into specific
8-bit XGMII codes as listed in
Channel Deskewing
The deskew FIFO in each of the four lanes expects to receive /A/ code group
simultaneously on all four channels during the inter-packet gap, as required by XAUI
protocol. The skew introduced in the physical medium and the receiver channels
might cause the /A/ code group to be received misaligned with respect to each other.
The deskew FIFO works to align the /A/ code group across the four channels, which
operation is compliant to the PCS deskew state machine diagram specified in
clause 48 of the IEEE P802.3ae specification. The deskew operation begins after link
synchronization is achieved on all four channels as indicated by the word aligner in
each channel. The following are the deskew FIFO operations:
■
■
■
00 through FF
Any other value
Until the first /A/ code group is received, the deskew FIFO read and write
pointers in each channel are not incremented.
After the first /A/ code group is received, the write pointer starts incrementing for
each word received but the read pointer is frozen.
When all the four channels received the /A/ code group within 10 recovered clock
cycles of each other, the read pointer of all four deskew FIFOs is released
simultaneously, aligning the /A/ code group of all four channels in a column.
9C
FD
07
07
FB
FE
FE
(3)
(3)
K28.0, K28.3, or K28.5
Invalid code group
PCS Code Group
Table
PCS Code Group
K28.5
K28.4
K27.7
K29.7
K30.7
Dxx,y
K30.7
1–22.
Normal data transmission
Cyclone IV Device Handbook, Volume 2
Received code group
Invalid XGMII character
Description
Idle in ||T||
Idle in ||I||
Sequence
Terminate
Error
Start
Description
1–65