EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 47

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Memory Blocks in Cyclone IV Devices
Memory Modes
© November 2009 Altera Corporation
Table 3–4
Table 3–4. Cyclone IV Devices M9K Block Mixed-Width Configurations (True Dual-Port Mode)
In true dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output “New
Data” at that location or “Old Data”. To choose the desired behavior, set the
Read-During-Write option to either New Data or Old Data in the RAM MegaWizard
Plug-In Manager in the Quartus II software. For more information about this
behavior, refer to
In true dual-port mode, you can access any memory location at any time from either
port A or port B. However, when accessing the same memory location from both
ports, you must avoid possible write conflicts. When you attempt to write to the same
address location from both ports at the same time, a write conflict happens. This
results in unknown data being stored to that address location. There is no conflict
resolution circuitry built into the Cyclone IV devices M9K memory blocks. You must
handle address conflicts external to the RAM block.
Figure 3–11
and read operation at port B. Registering the outputs of the RAM simply delays the q
outputs by one clock cycle.
8192
4096
2048
1024
512
1024
512
Read Port
× 16
× 18
× 1
× 2
× 4
× 8
× 9
lists the possible M9K block mixed-port width configurations.
shows true dual-port timing waveforms for the write operation at port A
8192
v
v
v
v
v
—
—
“Read-During-Write Operations” on page
× 1
4096
v
v
v
v
v
—
—
× 2
2048
v
v
v
v
v
—
—
× 4
Write Port
1024
v
v
v
v
v
—
—
× 8
512
Cyclone IV Device Handbook, Volume 1
v
v
v
v
v
—
—
× 16
3–15.
1024
v
v
—
—
—
—
—
× 9
512
v
v
—
—
—
—
—
× 18
3–11