EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 321

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Cyclone IV Transceivers Architecture
Calibration Block
Calibration Block
© December 2010 Altera Corporation
This block calibrates the OCT resistors and the analog portions of the transceiver
blocks to ensure that the functionality is independent of process, voltage, and
temperature (PVT) variations.
Figure 1–40
transceiver blocks.
Figure 1–40. Transceiver Calibration Blocks Location and Connection
Note to
(1) Transceiver block GXBL1 is only available for devices in F484 and larger packages.
The calibration block internally generates a constant internal reference voltage,
independent of PVT variations and uses this voltage and the external reference
resistor on the RREF pin to generate constant reference currents. The OCT calibration
circuit calibrates the OCT resistors present in the transceiver channels.
shows the calibration block diagram.
Figure 1–41. Input Signals to the Calibration Blocks
Notes to
(1) All transceiver channels use the same calibration block clock and power down signals.
(2) Connect a 2 k (tolerance max ± 1%) external resistor to the RREF pin to ground. The RREF resistor connection in
(3) Supports up to 125 MHz clock frequency. Use either dedicated global clock or divide-down logic from the FPGA fabric
(4) The calibration block restarts the calibration process following deassertion of the cal_blk_powerdown signal.
the board must be free from any external noise.
to generate a slow clock on the local clock routing.
cal_blk_powerdown (4)
Figure
OCT Calibration Control
Figure
1–40:
cal_blk_clk (3)
shows the location of the calibration block and how it is connected to the
1–41:
RREF pin (2)
2KΩ
OCT Calibration
Circuit
RREF
GXBL1 (1)
GXBL0
Calibration Block
Calibration
Block
Reference
Generator
Internal
Voltage
(Note 1)
Calibration Circuit
Cyclone IV GX
Analog Block
Device
Reference
Signal
Cyclone IV Device Handbook, Volume 2
Calibration Control
Analog Block
Figure 1–41
1–41