EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 346
![no-image](/images/manufacturer_photos/0/0/40/altera_sml.jpg)
EP4CGX150CF23I7N
Manufacturer Part Number
EP4CGX150CF23I7N
Description
IC CYCLONE IV FPGA 150K 484FBGA
Manufacturer
Altera
Series
CYCLONE® IV GXr
Datasheets
1.EP4CGX15BN11C8N.pdf
(44 pages)
2.EP4CGX15BN11C8N.pdf
(14 pages)
3.EP4CGX15BN11C8N.pdf
(478 pages)
4.EP4CGX15BN11C8N.pdf
(10 pages)
Specifications of EP4CGX150CF23I7N
Number Of Logic Elements/cells
149760
Number Of Labs/clbs
9360
Total Ram Bits
6480000
Number Of I /o
270
Voltage - Supply
1.16 V ~ 1.24 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
484-FBGA
Family Name
Cyclone IV
Number Of Logic Blocks/elements
149760
# I/os (max)
270
Operating Supply Voltage (typ)
1.2V
Logic Cells
149760
Ram Bits
6635520
Operating Supply Voltage (min)
1.16V
Operating Supply Voltage (max)
1.24V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
484
Package Type
FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP4CGX150CF23I7N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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1–66
Figure 1–65. Deskew FIFO–Lane Skew at the Receiver Input
Cyclone IV Device Handbook, Volume 2
Lane 0
Lane 2
K
Lane 1
Lane 3
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K
Lane 0
Lane 1
Lane 2
Lane 3
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K
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■
■
■
Figure 1–65
/A/ code group to align the channels.
Lane Synchronization
In XAUI mode, the word aligner is configured in automatic synchronization state
machine mode that is compliant to the PCS synchronization state diagram specified in
clause 48 of the IEEE P802.3ae specification.
machine parameters that implements the lane synchronization in XAUI mode.
Table 1–23. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 7-bit and 10-bit pattern lengths in XAUI mode.
K
K
K
K
Channel alignment is acquired if three additional aligned ||A|| columns are
observed at the output of the deskew FIFOs of the four channels after alignment of
the first ||A|| column.
Channel alignment is indicated by the assertion of rx_channelaligned signal.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at
the output of the deskew FIFOs in all four channels with no aligned ||A||
columns in between, the rx_channelaligned signal is deasserted, indicating
loss of channel alignment.
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A
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Table
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A
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1–23:
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shows lane skew at the receiver input and how the deskew FIFO uses the
/A/ column
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A
A
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Parameter
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Table 1–23
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Chapter 1: Cyclone IV Transceivers Architecture
(Note 1)
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lists the synchronization state
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© December 2010 Altera Corporation
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Transceiver Functional Modes
Lanes skew at
receiver input
Lanes are deskewed by lining
up the “Align”/A/ code groups
Value
4
4
4
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