EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 328

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–48
PCI Express (PIPE) Mode
.
Figure 1–48. Transceiver Channel Datapath and Clocking when Configured in PIPE Mode with ×1 Channel Configuration
Notes to
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
Cyclone IV Device Handbook, Volume 2
Fabric
FPGA
Figure 1–48
:
PIPE mode provides the transceiver channel datapath configuration that supports ×1,
×2, and ×4 initial lane width for PCIe Gen1 signaling rate with PIPE interface
implementation. The Cyclone IV GX transceiver provides following features in PIPE
mode:
■
■
■
■
■
■
■
■
■
■
■
Figure 1–48
PIPE mode with ×1 channel configuration.
Configuring the hard IP module requires using the PCI Express Compiler. When
configuring the transceiver for PCIe implementation with hard IP module, the byte
serializer and deserializer are not enabled, providing an 8-bit transceiver-PIPE-hard
IP data interface width running at 250 MHz clock frequency.
PIPE interface
receiver detection circuitry
electrical idle control
signal detect at receiver
lane synchronization with compliant state machine
clock rate compensation with rate match FIFO
Low-Latency Synchronous PCIe
fast recovery from P0s state
electrical idle inference
compliance pattern transmission
reset requirement
Phase
Comp
FIFO
Rx
shows the transceiver channel datapath and clocking when configured in
wr_clk
Tx Phase
Comp
FIFO
rd_clk
Order-
Byte
ing
/2
serializer
Byte
De-
wr_clk
Byte Serializer
/2
Transmitter Channel PCS
Decoder
8B/10B
Receiver Channel PCS
rd_clk
Match
FIFO
Rate
Chapter 1: Cyclone IV Transceivers Architecture
8B/10B Encoder
Deskew
FIFO
© December 2010 Altera Corporation
(1)
Transceiver Functional Modes
Aligner
Word
Deserial-
Transmitter Channel PMA
Receiver Channel PMA
izer
Serializer
(2)
CDR
low-speed clock
high-speed
clock
CDR clock