EP4CGX150CF23I7N Altera, EP4CGX150CF23I7N Datasheet - Page 104

• Manufacturer Part Number: EP4CGX150CF23I7N
• Description: IC CYCLONE IV FPGA 150K 484FBGA
• Manufacturer: Altera
• Series: CYCLONE® IV GXr

Specifications of EP4CGX150CF23I7N

• Number Of Logic Elements/cells: 149760
• Number Of Labs/clbs: 9360
• Total Ram Bits: 6480000
• Number Of I /o: 270
• Voltage - Supply: 1.16 V ~ 1.24 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 484-FBGA
• Family Name: Cyclone IV
• Number Of Logic Blocks/elements: 149760
• # I/os (max): 270
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 149760
• Ram Bits: 6635520
• Operating Supply Voltage (min): 1.16V
• Operating Supply Voltage (max): 1.24V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 484
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–42
Cyclone IV Device Handbook, Volume 1
f
To perform one dynamic phase shift step, follow these steps:
1. Set phaseupdown and phasecounterselect as required.
2. Assert phasestep for at least two scanclk cycles. Each phasestep pulse
3. De-assert phasestep.
4. Wait for phasedone to go high.
5. You can repeat steps
All signals are synchronous to scanclk, so they are latched on the scanclk edges
and must meet t
Figure 5–26. PLL Dynamic Phase Shift
Dynamic phase shifting can be repeated indefinitely. All signals are synchronous to
scanclk, so they must meet t
The phasestep signal is latched on the negative edge of scanclk. In
this is shown by the second scanclk falling edge. phasestep must stay high for at
least two scanclk cycles. On the second scanclk rising edge after phasestep is
latched (indicated by the fourth rising edge), the values of phaseupdown and
phasecounterselect are latched and the PLL starts dynamic phase shifting for the
specified counter or counters and in the indicated direction. On the fourth scanclk
rising edge, phasedone goes high to low and remains low until the PLL finishes
dynamic phase shifting. You can perform another dynamic phase shift after the
phasedone signal goes from low to high.
Depending on the VCO and scanclk frequencies, thephasedone low time may be
greater than or less than one scanclk cycle.
After phasedone goes from low to high, you can perform another dynamic phase
shift. phasestep pulses must be at least one scanclk cycle apart.
For information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager,
refer to the
enables one phase shift.
shifts.
phasecounterselect
ALTPLL_RECONFIG Megafunction User
phaseupdown
SU
phasestep
phasedone
or t
scanclk
H
requirements (with respect to the scanclk edges).
1
through
SU
or t
4
H
as many times as required to get multiple phase
requirements (with respect to scanclk edges).
Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Guide.
© December 2010 Altera Corporation
Figure
PLL Reconfiguration
5–26,