OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 61

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 60.
UM10441
User manual
Name
PIO0_6
PIO0_7
PIO0_8
PIO0_9
PIO2_0
PIO2_1
PIO2_2
PIO2_3
PIO2_4
PIO2_5
PIO2_6
PIO2_7
PIO0_10
PIO0_11
PIO0_12
RESET_PIO0_13
PIO0_14
PIO0_15
PIO0_16
PIO0_17
PIO0_18
R_PIO0_30
R_PIO0_31
R_PIO1_0
R_PIO1_1
PIO1_2
PIO1_3
PIO1_4
PIO1_5
PIO1_6
-
-
PIO2_8
PIO2_9
PIO2_10
PIO2_11
Register overview: I/O configuration block (base address 0x4004 4000)
Access Address
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
-
R/W
R/W
R/W
R/W
offset
0x060
0x064
0x068
0x06C
0x070
0x074
0x078
0x07C
0x080
0x084
0x088
0x08C
0x090
0x094
0x098
0x09C
0x0A0
0x0A4
0x0A8
0x0AC
0x0B0
0x0B4
0x0B8
0x0BC
0x0C0
0x0C4
0x0C8
0x0CC
0x0D0
0x0D4
0x0D8
0x0DC
0x0E0
0x0E4
0x0E8
0x0EC
All information provided in this document is subject to legal disclaimers.
Description
Configures pin PIO0_6/RI0/CT32B1_0.
Configures pin PIO0_7CTS0/CT32B1_1.
Configures pin PIO0_8/RXD1/CT32B1_2.
Configures pin PIO0_9/TXD1/CT32B1_3.
Configures pin PIO2_0/CT16B0_0/RTS0.
Configures pin PIO2_1/CT16B0_1/RXD0.
Configures pin PIO2_2/CT16B1_0/TXD0.
Configures pin PIO2_3/CT16B1_1/DTR0.
Configures pin PIO2_4/CT32B0_0/CTS0.
Configures pin PIO2_5/CT32B0_1/DCD0.
Configures pin PIO2_6/CT32B0_2/RI0.
Configures pin PIO2_7/CT32B0_3/DSR0.
Configures pin PIO0_10/SCL.
Configures pin PIO0_11/SDA/CT16B0_0.
Configures pin
PIO0_12/CLKOUT/CT16B0_1.
Configures pin RESET/PIO0_13.
Configures pin PIO0_14/SSP_CLK.
Configures pin
PIO0_15/SSP_SSEL/CT16B1_0.
Configures pin
PIO0_16/SSP_MISO/CT16B1_1.
Configures pin PIO0_17/SSP_MOSI.
Configures pin PIO0_18/SWCLK/CT32B0_0. 0x0000 0090
Configures pin R/PIO0_30/AD0.
Configures pin R/PIO0_31/AD1.
Configures pin R/PIO1_0/AD2.
Configures pin R/PIO1_1/AD3.
Configures pin PIO1_2/SWDIO/AD4.
Configures pin PIO1_3/AD5/WAKEUP.
Configures pin PIO1_4/AD6
Configures pin PIO1_5/AD7/CT16B1_0.
Configures pin PIO1_6/CT16B1_1.
Reserved.
Reserved.
Configures pin PIO2_8/CT32B1_0.
Configures pin PIO2_9/CT32B1_1.
Configures pin PIO2_10/CT32B1_2/TXD1.
Configures pin PIO2_11/CT32B1_3/RXD1.
Rev. 1.1 — 10 March 2011
Chapter 6: LPC122x I/O configuration (IOCONFIG)
…continued
Reset value
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0080
0x0000 0080
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
-
-
0x0000 0090
0x0000 0090
0x0000 0090
0x0000 0090
UM10441
© NXP B.V. 2011. All rights reserved.
Reference
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