OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 386

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.4.4.1.3 Restrictions
25.4.4.1.4 Condition flags
25.4.4.1.5 Examples
25.4.4.2.1 Syntax
25.4.4.2.2 Operation
25.4.4.2.3 Restrictions
25.4.4.2 LDR and STR, immediate offset
ADR facilitates the generation of position-independent code, because the address is
PC-relative.
If you use ADR to generate a target address for a BX or BLX instruction, you must ensure
that bit[0] of the address you generate is set to 1 for correct execution.
In this instruction Rd must specify R0-R7. The data-value addressed must be word
aligned and within 1020 bytes of the current PC.
This instruction does not change the flags.
Load and Store with immediate offset.
LDR Rt, [<Rn | SP> {, #imm}]
LDR<B|H> Rt, [Rn {, #imm}]
STR Rt, [<Rn | SP>, {,#imm}]
STR<B|H> Rt, [Rn {,#imm}]
where:
LDR, LDRB and LDRH instructions load the register specified by Rt with either a word,
byte or halfword data value from memory. Sizes less than word are zero extended to
32-bits before being written to the register specified by Rt.
STR, STRB and STRH instructions store the word, least-significant byte or lower halfword
contained in the single register specified by Rt in to memory. The memory address to load
from or store to is the sum of the value in the register specified by either Rn or SP and the
immediate value imm.
In these instructions:
•
Rt is the register to load or store.
Rn is the register on which the memory address is based.
imm is an offset from Rn. If imm is omitted, it is assumed to be zero.
ADR
ADR
Rt and Rn must only specify R0-R7.
R1, TextMessage
R3, [PC,#996]
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
; Write address value of a location labelled as
; Set R3 to value of PC + 996.
; TextMessage to R1
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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