OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 420

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.5.3.8 SCB usage hints and tips
25.5.4.1 SysTick Control and Status Register
25.5.4 System timer, SysTick
Table 390. SHPR3 register bit assignments
Ensure software uses aligned 32-bit word size transactions to access all the SCB
registers.
When enabled, the timer counts down from the reload value to zero, reloads (wraps to)
the value in the SYST_RVR on the next clock cycle, then decrements on subsequent
clock cycles. Writing a value of zero to the SYST_RVR disables the counter on the next
wrap. When the counter transitions to zero, the COUNTFLAG status bit is set to 1.
Reading SYST_CSR clears the COUNTFLAG bit to 0.
Writing to the SYST_CVR clears the register and the COUNTFLAG status bit to 0. The
write does not trigger the SysTick exception logic. Reading the register returns its value at
the time it is accessed.
Remark: When the processor is halted for debugging the counter does not decrement.
The system timer registers are:
Table 391. System timer registers summary
[1]
The SYST_CSR enables the SysTick features. See the register summary in for its
attributes. The bit assignments are:
Table 392. SYST_CSR bit assignments
Bits
[31:24]
[23:16]
[15:0]
Address
0xE000E010
0xE000E014
0xE000E018
0xE000E01C
Bits
[31:17]
[16]
[15:3]
SysTick calibration value.
Name
-
COUNTFLAG
-
Name
PRI_15
PRI_14
-
Name
SYST_CSR
SYST_RVR
SYST_CVR
SYST_CALIB RO
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Function
Priority of system handler 15, SysTick exception
Priority of system handler 14, PendSV
Reserved
Function
Reserved.
Returns 1 if timer counted to 0 since the last read of this register.
Reserved.
RW
Type
RW
RW
Reset
value
0x00000000
Unknown
Unknown
0xC0000000
Chapter 25: LPC122x Appendix ARM Cortex-M0
[1]
Description
Section 25.5.4.1
Section 25–25.5.4.2
Section 25–25.5.4.3
Section 25–25.5.4.4
UM10441
© NXP B.V. 2011. All rights reserved.
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