OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 249

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
13.7.11 Count Control Register
If the EMR bits are set to 10 or 11 for channel 0 (rising edge or toggle), a DMA request is
generated even if the corresponding MR register is set to 0 because a match-on-zero
condition exists. To disable any DMA requests, set the EMR bits for channel 0 to 00.
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting.
When Counter Mode is chosen as a mode of operation, the CAP input (selected by the
CTCR bits 3:2) is sampled on every rising edge of the PCLK clock. After comparing two
consecutive samples of this CAP input, one of the following four events is recognized:
rising edge, falling edge, either of edges or no changes in the level of the selected CAP
input. Only if the identified event occurs, and the event corresponds to the one selected by
bits 1:0 in the CTCR register, will the Timer Counter register be incremented.
Effective processing of the externally supplied clock to the counter has some limitations.
Since two successive rising edges of the PCLK clock are used to identify only one edge
on the CAP selected input, the frequency of the CAP input can not exceed one half of the
PCLK clock. Consequently, the duration of the HIGH/LOW levels on the same CAP input
in this case can not be shorter than 1/PCLK.
Bits 7:4 of this register are also used to enable and configure the capture-clears-timer
feature. This feature allows for a designated edge on a particular CAP input to reset the
timer to all zeros. Using this mechanism to clear the timer on the leading edge of an input
pulse and performing a capture on the trailing edge, permits direct pulse-width
measurement using a single capture input without the need to perform a subtraction
operation in software.
Table 231. Count Control Register (CTCR, address 0x4001 0070 (CT16B0) and 0x4001 4070
Bit
1:0
Symbol
CTM
(CT16B1)) bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
Rev. 1.1 — 10 March 2011
Description
Counter/Timer Mode. This field selects which rising PCLK
edges can increment Timer’s Prescale Counter (PC), or clear
PC and increment Timer Counter (TC).
Remark: If Counter mode is selected in the CTCR, bits 2:0 in
the Capture Control Register (CCR) must be programmed as
000.
Timer Mode: every rising PCLK edge
Counter Mode: TC is incremented on rising edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on falling edges on the
CAP input selected by bits 3:2.
Counter Mode: TC is incremented on both edges on the CAP
input selected by bits 3:2.
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
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Reset
value
00