OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 178

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
10.6 Architecture
UM10441
User manual
10.5.14 UART FIFO Level register
Although
control, it is strongly suggested to let UART hardware implemented auto flow control
features take care of this, and limit the scope of TXEn to software flow control.
TER enables implementation of software and hardware flow control. When TXEn =1,
UART transmitter will keep sending data as long as they are available. As soon as TXEn
becomes 0, UART transmission will stop.
Table 178
Table 178. UART Transmit Enable Register (TER - address 0x4000 C030) bit description
FIFOLVL register is a Read Only register that allows software to read the current FIFO
level status. Both the transmit and receive FIFO levels are present in this register.
Table 179. UART FIFO Level register (FIFOLVL - address 0x4000 C058, Read Only) bit
The architecture of the UART is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART.
The UART receiver block, RX, monitors the serial input line, RXD, for valid input. The
UART RX Shift Register (RSR) accepts valid characters via RXD. After a valid character is
assembled in the RSR, it is passed to the UART RX Buffer Register FIFO to await access
by the CPU or host via the generic host interface.
Bit
6:0
7
31:8 -
Bit
3:0
7:4
11:8
31:12
Symbol
-
TXEN
Table 178
Symbol
RXFIFILVL
-
TXFIFOLVL
-
describes how to use TXEn bit in order to achieve software flow control.
description
All information provided in this document is subject to legal disclaimers.
Description
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
When this bit is 1, as it is after a Reset, data written to the THR
is output on the TXD pin as soon as any preceding data has
been sent. If this bit cleared to 0 while a character is being sent,
the transmission of that character is completed, but no further
characters are sent until this bit is set again. In other words, a 0
in this bit blocks the transfer of characters from the THR or TX
FIFO into the transmit shift register. Software can clear this bit
when it receives an XOFF character (DC3). Software can set
this bit again when it receives an XON (DC1) character.
Reserved
describes how to use TXEn bit in order to achieve hardware flow
Rev. 1.1 — 10 March 2011
Description
Reflects the current level of the UART receiver FIFO.
0 = empty, 0xF = FIFO full.
Reserved. The value read from a reserved bit is not defined.
0 = empty, 0xF = FIFO full.
Reflects the current level of the UART transmitter FIFO.
Reserved. The value read from a reserved bit is not defined.
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
NA
1
-
178 of 442
Reset
value
0x00
-
0x00
NA