OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 268

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OM13008,598

Manufacturer Part Number
OM13008,598
Description
BOARD LPC XPRESSO LPC122X
Manufacturer
NXP Semiconductors
Series
LPCXpressor
Datasheets

Specifications of OM13008,598

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-6642
OM13008
NXP Semiconductors
14.8 Example timer operation
14.9 Architecture
UM10441
User manual
Fig 42. A timer cycle in which PR=2, MRx=6, and both interrupt and reset on match are enabled
Fig 43. A timer cycle in which PR=2, MRx=6, and both interrupt and stop on match are enabled
prescale counter
timer counter
(counter enable)
timer counter
prescale
interrupt
counter
counter
PCLK
timer
reset
interrupt
TCR[0]
PCLK
Figure 42
The prescaler is set to 2 and the match register set to 6. At the end of the timer cycle
where the match occurs, the timer count is reset. This gives a full length cycle to the
match value. The interrupt indicating that a match occurred is generated in the next clock
after the timer reached the match value.
Figure 43
prescaler is again set to 2 and the match register set to 6. In the next clock after the timer
reaches the match value, the timer enable bit in TCR is cleared, and the interrupt
indicating that a match occurred is generated.
The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in
Figure
4
2
4
2
44.
shows a timer configured to reset the count and generate an interrupt on match.
shows a timer configured to stop and generate an interrupt on match. The
0
0
All information provided in this document is subject to legal disclaimers.
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Rev. 1.1 — 10 March 2011
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Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
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UM10441
© NXP B.V. 2011. All rights reserved.
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