OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 266

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
14.7.12 PWM Control Register
Table 247: Count Control Register (CTCR, address 0x4001 8070 (CT32B0) and 0x4001 C070
The PWM Control Register is used to configure the match outputs as PWM outputs. Each
match output can be independently set to perform either as PWM output or as match
output whose function is controlled by the External Match Register (EMR).
For each timer, a maximum of three single edge controlled PWM outputs can be selected
on the MATn.2:0 outputs. One additional match register determines the PWM cycle
length. When a match occurs in any of the other match registers, the PWM output is set to
HIGH. The timer is reset by the match register that is configured to set the PWM cycle
length. When the timer is reset to zero, all currently HIGH match outputs configured as
PWM outputs are cleared.
Table 248: PWM Control Register (PWMC, 0x4001 8074 (CT32B0) and 0x4001 C074 (CT32B1))
Bit
7:5
31:8
Bit
0
1
2
Symbol
SElCC
-
Symbol
PWMEN0
PWMEN1
PWMEN2
(CT32B1)) bit description
bit description
All information provided in this document is subject to legal disclaimers.
Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-
Value
0
1
0
1
0
1
Rev. 1.1 — 10 March 2011
Description
When bit 4 is a 1, these bits select which capture input edge
will cause the timer and prescaler to be cleared. These bits
have no effect when bit 4 is low.
Rising Edge of CAP0 clears the timer (if bit 4 is set)
Falling Edge of CAP0 clears the timer (if bit 4 is set)
Rising Edge of CAP1 clears the timer (if bit 4 is set)
Falling Edge of CAP1 clears the timer (if bit 4 is set)
Rising Edge of CAP2 clears the timer (if bit 4 is set)
Falling Edge of CAP2 clears the timer (if bit 4 is set)
Rising Edge of CAP3 clears the timer (if bit 4 is set)
Falling Edge of CAP3 clears the timer (if bit 4 is set)
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
Description
PWM mode enable for channel0.
CT32Bi_MAT0 is controlled by EM0.
PWM mode is enabled for CT32Bi_MAT0.
PWM mode enable for channel1.
CT32Bi_MAT01 is controlled by EM1.
PWM mode is enabled for CT32Bi_MAT1.
PWM mode enable for channel2.
CT32Bi_MAT2 is controlled by EM2.
PWM mode is enabled for CT32Bi_MAT2.
…continued
UM10441
© NXP B.V. 2011. All rights reserved.
266 of 442
Reset
value
0
0
0
Reset
value
-