OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 375

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.3.5.1.1 Wait for interrupt
25.3.5.1.2 Wait for event
25.3.5.1 Entering sleep mode
25.3.5 Power management
If lockup state occurs in the NMI handler a subsequent NMI does not cause the processor
to leave lockup state.
The Cortex-M0 processor sleep modes reduce power consumption:
The SLEEPDEEP bit of the SCR selects which sleep mode is used, see
Section
This section describes the mechanisms for entering sleep mode, and the conditions for
waking up from sleep mode.
This section describes the mechanisms software can use to put the processor into sleep
mode.
The system can generate spurious wakeup events, for example a debug operation wakes
up the processor. Therefore software must be able to put the processor back into sleep
mode after such an event. A program might have an idle loop to put the processor back in
to sleep mode.
The Wait For Interrupt instruction, WFI, causes immediate entry to sleep mode. When the
processor executes a WFI instruction it stops executing instructions and enters sleep
mode. See
Remark: The WFE instruction is not implemented on the LPC11U1x.
The Wait For Event instruction, WFE, causes entry to sleep mode conditional on the value
of a one-bit event register. When the processor executes a WFE instruction, it checks the
value of the event register:
0 — The processor stops executing instructions and enters sleep mode
1 — The processor sets the register to zero and continues executing instructions without
entering sleep mode.
See
If the event register is 1, this indicates that the processor must not enter sleep mode on
execution of a WFE instruction. Typically, this is because of the assertion of an external
event, or because another processor in the system has executed a SEV instruction, see
Section
•
•
a sleep mode, that stops the processor clock
a Deep-sleep mode, details <tbd>.
Section 25–25.4.7.11
25–25.5.3.5.
25–25.4.7.9. Software cannot access this register directly.
Section 25–25.4.7.12
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
for more information.
for more information.
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
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