OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 409

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
25.5 Peripherals
UM10441
User manual
25.4.7.12.5 Examples
25.5.1 About the ARM Cortex-M0
25.5.2 Nested Vectored Interrupt Controller
The address map of the Private peripheral bus (PPB) is:
Table 373. Core peripheral register regions
In register descriptions, the register type is described as follows:
RW — Read and write.
RO — Read-only.
WO — Write-only.
This section describes the Nested Vectored Interrupt Controller (NVIC) and the
registers it uses. The NVIC supports:
The processor automatically stacks its state on exception entry and unstacks this state on
exception exit, with no instruction overhead. This provides low latency exception handling.
The hardware implementation of the NVIC registers is:
Table 374. NVIC register summary
Address
0xE000E008-0xE000E00F
0xE000E010-0xE000E01F
0xE000E100-0xE000E4EF
0xE000ED00-0xE000ED3F
0xE000EF00-0xE000EF03
Address
0xE000E100
0xE000E180
0xE000E200
0xE000E280
0xE000E400-0x
E000E41C
•
•
•
•
•
WFI ; Wait for interrupt
32 interrupts.
A programmable priority level of 0-3 for each interrupt. A higher level corresponds to a
lower priority, so level 0 is the highest interrupt priority.
Level and pulse detection of interrupt signals.
Interrupt tail-chaining.
An external Non-maskable interrupt (NMI).
Name
ISER
ICER
ISPR
ICPR
IPR0-7
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Core peripheral
System Control Block
System timer
Nested Vectored Interrupt Controller
System Control Block
Nested Vectored Interrupt Controller
Type
RW
RW
RW
RW
RW
Chapter 25: LPC122x Appendix ARM Cortex-M0
Reset value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Section 25–25.5.2.2
Section 25–25.5.2.3
Section 25–25.5.2.4
Section 25–25.5.2.5
Section 25–25.5.2.6
Description
Table 25–382
Table 25–391
Table 25–374
Table 25–382
Table 25–374
UM10441
© NXP B.V. 2011. All rights reserved.
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