OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 362

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.3.1.3.6 Exception mask register
25.3.1.3.7 CONTROL register
Table 357. EPSR bit assignments
Attempts by application software to read the EPSR directly using the MRS instruction
always return zero. Attempts to write the EPSR using the MSR instruction are ignored. Fault
handlers can examine the EPSR value in the stacked PSR to determine the cause of the
fault. See
Attempting to execute instructions when the T bit is 0 results in a HardFault or lockup. See
Section 25–25.3.4.1
Interruptible-restartable instructions:
and STM. When an interrupt occurs during the execution of one of these instructions, the
processor abandons execution of the instruction.
After servicing the interrupt, the processor restarts execution of the instruction from the
beginning.
The exception mask register disables the handling of exceptions by the processor.
Disable exceptions where they might impact on timing critical tasks or code sequences
requiring atomicity.
To disable or re-enable exceptions, use the MSR and MRS instructions, or the CPS instruction,
to change the value of PRIMASK. See
Section 25–25.4.7.2
Priority Mask Register:
configurable priority. See the register summary in
assignments are:
Table 358. PRIMASK register bit assignments
The CONTROL register controls the stack used when the processor is in Thread mode.
See the register summary in
Bits
[31:25]
[24]
[23:0]
Bits
[31:1]
[0]
•
•
•
instructions BLX, BX and POP{PC}
restoration from the stacked xPSR value on an exception return
bit[0] of the vector value on an exception entry.
Section
All information provided in this document is subject to legal disclaimers.
25–25.3.3.6. The following can clear the T bit to 0:
Name
-
PRIMASK
for more information.
for more information.
Rev. 1.1 — 10 March 2011
The PRIMASK register prevents activation of all exceptions with
Table 25–353
Name
-
T
-
Function
Reserved
0 = no effect
1 = prevents the activation of all exceptions with
configurable priority.
Chapter 25: LPC122x Appendix ARM Cortex-M0
Section
The interruptible-restartable instructions are LDM
for its attributes. The bit assignments are:
25–25.4.7.6,
Table 25–353
Function
Reserved
Thumb state bit
Reserved
Section
for its attributes. The bit
25–25.4.7.7, and
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