OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 341

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.7.4.3 Auto-request cycle
21.7.4.4 Ping-pong cycle
When the controller operates in this mode, it is only necessary for it to receive a single
request to enable it to complete the entire DMA cycle. This enables a large data transfer
to occur, without significantly increasing the latency for servicing higher priority requests
or requiring multiple requests from the processor or peripheral.
The auto-request cycle is typically used for memory-to-memory requests. In this case,
software generates the starting request for the 2
control data structure.
In this mode, the controller can be configured to use either the primary or the alternate
channel control data structure. After the channel is enabled and the controller receives a
request for this channel, the flow for the auto-request cycle is as follows:
In this mode, the controller performs a DMA cycle using one of the data structures and
then performs a DMA cycle using the other data structure. The controller continues to
switch between primary and alternate structures until it reads a data structure that is
invalid, until the user reprograms the cycle_type to basic, or until the host processor
disables the channel.
In ping-pong mode, the user can program or reprogram one of the two channel data
structures (primary or alternate) while using the other channel data structure for the active
transfer. When a transfer is done, the next transfer can be started immediately using the
prepared channel data structure - provided that a higher priority channel does not require
servicing. If the user does not reprogram the channel control data structure not in use for
a transfer, the cycle type remains invalid (which is the value at the end of the last transfer
using that structure), and the ping-pong cycle completes.
The ping-pong cycle can be used for transfers to or from peripherals or for
memory-to-memory transfers.
3. The controller sets dma_done[c] signal for this channel HIGH for one system clock
1. The controller performs 2
2. The controller arbitrates if there are any transfers remaining after 2
3. The controller sets dma_done[c] signal for this channel HIGH for one system clock
cycle. This indicates to the host processor that the DMA cycle is complete.
flow continues at step 3.
current channel c has the highest priority, the cycle continues at step 1.
cycle. This indicates to the host processor that the DMA cycle is complete.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
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transfers. If the number of transfers remaining is zero the
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transfers after setting up the DMA
UM10441
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© NXP B.V. 2011. All rights reserved.
transfers. If the
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