OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 263

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 245: External Match Register (EMR, address 0x4001 803C (CT32B0) and 0x4001 C03C (CT32B1)) bit
UM10441
User manual
Bit
0
1
2
3
5:4
7:6
9:8
11:10 EMC3
Symbol
EM0
EM1
EM2
EM3
EMC0
EMC1
EMC2
description
Value Description
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
0x2
0x3
0x0
0x1
External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this
output is connected to its pin. When a match occurs between the TC and MR0, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the
functionality of this output. This bit is driven to the CT32B0_MAT0/CT32B1_MAT0 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this
output is connected to its pin. When a match occurs between the TC and MR1, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the
functionality of this output. This bit is driven to the CT32B0_MAT1/CT32B1_MAT1 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this
output is connected to its pin. When a match occurs between the TC and MR2, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the
functionality of this output. This bit is driven to the CT32B0_MAT2/CT32B1_MAT2 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this
output is connected to its pin. When a match occurs between the TC and MR3, this bit
can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the
functionality of this output. This bit is driven to the CT32B3_MAT0/CT32B1_MAT3 pins if
the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).
External Match Control 0. Determines the functionality of External Match 0.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT0 pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT0 pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 1. Determines the functionality of External Match 1.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT1 pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT1 pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 2. Determines the functionality of External Match 2.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT2 pin is LOW if
pinned out).
Set the corresponding External Match bit/output to 1 (CT32Bi_MAT2 pin is HIGH if
pinned out).
Toggle the corresponding External Match bit/output.
External Match Control 3. Determines the functionality of External Match 3.
Do Nothing.
Clear the corresponding External Match bit/output to 0 (CT32Bi_MAT3 pin is LOW if
pinned out).
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
263 of 442
Reset
value
0
0
0
0
00
00
00
00