OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 425

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
26.4 Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. System PLL control register (SYSPLLCTRL,
Table 11. System PLL status register (SYSPLLSTAT,
Table 12. System oscillator control register (SYSOSCCTRL,
Table 13. Watchdog oscillator control register
Table 14. Internal resonant crystal control register
Table 15. System reset status register (SYSRESSTAT,
Table 16. System PLL clock source select register
Table 17. System PLL clock source update enable register
Table 18. Main clock source select register (MAINCLKSEL,
Table 19. Main clock source update enable register
Table 20. System AHB clock divider register
Table 21. System AHB clock control register
Table 22. SSP clock divider register (SSPCLKDIV, address
Table 23. UART0 clock divider register (UART0CLKDIV,
Table 24. UART1 clock divider register (UART1CLKDIV,
Table 25. RTC clock divider register (RTCCLKDIV, address
Table 26. CLKOUT clock source select register
UM10441
User manual
Ordering information . . . . . . . . . . . . . . . . . . . . .5
Ordering options for LPC122x . . . . . . . . . . . . . .5
LPC122x memory configuration . . . . . . . . . . . . .7
Connection of interrupt sources to the Vectored
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . .9
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Register overview: system control block (base
address 0x4004 8000) . . . . . . . . . . . . . . . . . .13
Register overview: flash configuration (base
address 0x5006 8000) . . . . . . . . . . . . . . . . . .15
System memory remap register
(SYSMEMREMAP, address 0x4004 8000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Peripheral reset control register (PRESETCTRL,
address 0x4004 8004) bit description. . . . . . . .16
address 0x4004 8008) bit description . . . . . . .17
address 0x4004 800C) bit description . . . . . . .17
address 0x4004 8020) bit description. . . . . . . .18
(WDTOSCCTRL, address 0x4004 8024) bit
description
(IRCCTRL, address 0x4004 8028) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
address 0x4004 8030) bit description. . . . . . . .19
(SYSPLLCLKSEL, address 0x4004 8040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
(SYSPLLCLKUEN, address 0x4004 8044) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
address 0x4004 8070) bit description. . . . . . . .21
(MAINCLKUEN, address 0x4004 8074) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
(SYSAHBCLKDIV, address 0x4004 8078) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
(SYSAHBCLKCTRL, address 0x4004 8080) bit
description
0x4004 8094) bit description . . . . . . . . . . . . . .24
address 0x4004 8098) bit description. . . . . . . .25
address 0x4004 809C) bit description . . . . . . .25
0x4004 80A0) bit description . . . . . . . . . . . . . .25
(CLKOUTCLKSEL, address 0x4004 80E0) bit
. . . . . . . . . . . . . . . . . . . . . . . . . . .18
. . . . . . . . . . . . . . . . . . . . . . . . . . .22
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table 27. CLKOUT clock source update enable register
Table 28. CLKOUT clock divider registers (CLKOUTDIV,
Table 29. POR captured PIO status registers 0
Table 30. POR captured PIO status registers 1
Table 31. IOCONFIG filter clock divider registers 0 to 6
Table 32. BOD control register (BODCTRL, address 0x4004
Table 33. System tick timer calibration register
Table 34. AHB matrix master priority register (AHBPRIO,
Table 35. IRQ latency register (IRQLATENCY, address
Table 36. NMI interrupt source configuration register
Table 37. Start logic edge control register 0 (STARTAPRP0,
Table 38. Start logic signal enable register 0 (STARTERP0,
Table 39. Start logic reset register 0 (STARTRSRP0CLR,
Table 40. Start logic status register 0 (STARTSRP0,
Table 41. Start logic bit connection to peripheral interrupts .
Table 42. Start logic edge control register 1 (STARTAPRP1,
Table 43. Start logic signal enable register 1 (STARTERP1,
Table 44. Start logic reset register 1 (STARTRSRP1CLR,
Table 45. Start logic signal status register 1 (STARTSRP1,
Table 46. Allowed values for PDSLEEPCFG register if
Table 47. Allowed values for PDSLEEPCFG register if
Table 48. Deep-sleep configuration register
Table 49. Wake-up configuration register (PDAWAKECFG,
Table 50. Power-down configuration register (PDRUNCFG,
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
(CLKOUTUEN, address 0x4004 80E4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
address 0x4004 80E8) bit description . . . . . . . 26
(PIOPORCAP0, address 0x4004 8100) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(PIOPORCAP1, address 0x4004 8104) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
(IOCONFIGCLKDIV0 to IOCONFIGCLKDIV6,
address 4004 8014C to 4004 80134) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8150) bit description. . . . . . . . . . . . . . . . . . . . . 28
(SYSTCKCAL, address 0x4004 8154) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
address 0x4004 8158) bit description . . . . . . . 29
0x4004 8170) bit description . . . . . . . . . . . . . . 29
(INTNMI, address 0x4004 8174) bit description30
address 0x4004 8200) bit description . . . . . . 30
address 0x4004 8204) bit description . . . . . . 31
address 0x4004 8208) bit description . . . . . . 33
address 0x4004 820C) bit description . . . . . . 34
35
address 0x4004 8210) bit description . . . . . . 36
address 0x4004 8214) bit description . . . . . . 37
address 0x4004 8218) bit description . . . . . . 38
address 0x4004 821C) bit description . . . . . . 40
WDLOCKCLK = 0 (WD oscillator not locked) . 41
WDLOCKCLK = 1 (WD oscillator locked) . . . . 41
(PDSLEEPCFG, address 0x4004 8230) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
address 0x4004 8234) bit description . . . . . . 43
address 0x4004 8238) bit description . . . . . . 44
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
425 of 442