OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 47

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
4.7.2.1 Power configuration in Sleep mode
4.7.2.2 Programming Sleep mode
4.7.2.3 Wake-up from Sleep mode
4.7.2 Sleep mode
4.7.3 Deep-sleep mode
In Sleep mode, the system clock to the ARM Cortex-M0 core is stopped, and execution of
instructions is suspended until either a reset or an enabled interrupt occurs.
Peripheral functions, if selected to be clocked in the SYSAHBCLKCTRL register, continue
operation during Sleep mode and may generate interrupts to cause the processor to
resume execution. Sleep mode eliminates dynamic power used by the processor itself,
memory systems and their related controllers, and internal buses. The processor state
and registers, peripheral registers, and internal SRAM values are maintained, and the
logic levels of the pins remain static.
Power consumption in Sleep mode is configured by the same settings as in Active mode:
The following steps must be performed to enter Sleep mode:
Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the
processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns
to its original power configuration defined by the contents of the PDRUNCFG and the
SYSAHBCLKDIV registers. If a reset occurs, the microcontroller enters the default
configuration in Active mode.
In Deep-sleep mode, the system clock to the processor is disabled as in Sleep mode. All
analog blocks are powered down, except for the BOD circuit and the watchdog oscillator,
which must be selected or deselected during Deep-sleep mode in the PDSLEEPCFG
register. The RTC and the RTC oscillator are operating in Deep-sleep mode unless the
RTC is powered down.
1. The DPDEN bit in the PCON register must be set to zero
2. The SLEEPDEEP bit in the ARM Cortex-M0 SCR register must be set to zero, see
3. Use the ARM Cortex-M0 Wait-For-Interrupt (WFI) instruction.
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The clock source for the system clock can be selected from the IRC (default), the
system oscillator, or the watchdog oscillator (see
The system clock frequency can be selected by the SYSPLLCTRL
SYSAHBCLKDIV register
Selected peripherals (UART, SSP0/1, WDT) use individual peripheral clocks with their
own clock dividers. The peripheral clocks can be shut down through the
corresponding clock divider registers
The clock remains running.
The system clock frequency remains the same as in Active mode, but the processor is
not clocked.
Analog and digital peripherals are selected as in Active mode.
(Table
386).
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
(Table
21).
Chapter 4: LPC122x System control (SYSCON)
(Table 22
to
Figure 3
Table
28).
(Table
and related registers).
56).
UM10441
(Table
© NXP B.V. 2011. All rights reserved.
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