OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 302

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
20.4 Applications
20.5 Description
UM10441
User manual
20.5.1 Memory map after any reset
The boot loader provides both In-System and In-Application programming interfaces for
programming the on-chip flash memory.
The boot loader code is executed every time the part is powered on or reset. The loader
can execute the ISP command handler or the user application code. A LOW level after
reset at the PIO0_12 pin is considered as an external hardware request to start the ISP
command handler. Assuming that power supply pins are on their nominal levels when the
rising edge on RESET pin is generated, it may take up to 3 ms before PIO0_12 is
sampled and the decision on whether to continue with user code or ISP handler is made.
If PIO0_12 is sampled low and the watchdog overflow flag is set, the external hardware
request to start the ISP command handler is ignored. If there is no request for the ISP
command handler execution (PIO0_12 is sampled HIGH after reset), a search is made for
a valid user program. If a valid user program is found then the execution control is
transferred to it. If a valid user program is not found, the auto-baud routine is invoked.
Pin PIO0_12 that is used as hardware request for ISP requires special attention. Since
PIO0_12 is in high impedance mode after reset, it is important that the user provides
external hardware (a pull-up resistor or other device) to put the pin in a defined state.
Otherwise unintended entry into ISP mode may occur.
The boot block is 8 kB in size. The boot block is located in the memory region starting
from the address 0x1FFF 0000. The boot loader is designed to run from this memory
area, but both the ISP and IAP software use parts of the on-chip RAM. The RAM usage is
described later in this chapter. The interrupt vectors residing in the boot block of the
on-chip flash memory also become active after reset, i.e., the bottom 512 bytes of the
boot block are also visible in the memory region starting from the address 0x0000 0000.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 20: LPC122x Flash ISP/IAP
UM10441
© NXP B.V. 2011. All rights reserved.
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