OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 435

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
8.2.1
8.3
8.3.1
8.3.2
8.3.3
8.3.4
8.3.5
8.3.6
Chapter 9: LPC122x UART0 with modem control
9.1
9.2
9.3
9.4
9.5
9.5.1
9.5.2
9.5.3
9.5.4
9.5.5
9.5.6
9.5.6.1
9.5.6.1.1 UART receiver DMA . . . . . . . . . . . . . . . . . . . 143
9.5.6.1.2 UART transmitter DMA . . . . . . . . . . . . . . . . . 143
9.5.7
9.5.8
9.5.8.1
9.5.8.1.1 Auto-RTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
9.5.8.1.2 Auto-CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
9.5.9
9.5.10
Chapter 10: LPC122x UART1
10.1
10.2
10.3
10.4
10.5
10.5.1
10.5.2
10.5.3
10.5.4
10.5.5
10.5.6
10.5.6.1
10.5.6.1.1 UART receiver DMA . . . . . . . . . . . . . . . . . . . 167
10.5.6.1.2 UART transmitter DMA. . . . . . . . . . . . . . . . . 167
UM10441
User manual
Register description . . . . . . . . . . . . . . . . . . . 130
How to read this chapter . . . . . . . . . . . . . . . . 136
Basic configuration . . . . . . . . . . . . . . . . . . . . 136
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 136
Register description . . . . . . . . . . . . . . . . . . . 137
How to read this chapter . . . . . . . . . . . . . . . . 160
Basic configuration . . . . . . . . . . . . . . . . . . . . 160
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 160
Register description . . . . . . . . . . . . . . . . . . . 160
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
GPIO mask register . . . . . . . . . . . . . . . . . . . 131
GPIO pin value register . . . . . . . . . . . . . . . . 131
GPIO pin output register . . . . . . . . . . . . . . . . 132
GPIO pin output set register . . . . . . . . . . . . . 132
GPIO pin output clear register . . . . . . . . . . . 133
GPIO NOT register . . . . . . . . . . . . . . . . . . . . 133
UART Receiver Buffer Register (when DLAB = 0,
Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 138
UART Transmitter Holding Register (when
DLAB = 0, Write Only) . . . . . . . . . . . . . . . . . 138
UART Divisor Latch LSB and MSB Registers
(when DLAB = 1) . . . . . . . . . . . . . . . . . . . . . 138
UART Interrupt Enable Register (when
DLAB = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
UART Interrupt Identification Register . . . . . 140
UART FIFO Control Register . . . . . . . . . . . . 142
DMA Operation . . . . . . . . . . . . . . . . . . . . . . . 142
UART Line Control Register . . . . . . . . . . . . . 143
UART Modem Control Register . . . . . . . . . . 143
Auto-flow control . . . . . . . . . . . . . . . . . . . . . . 144
UART Line Status Register. . . . . . . . . . . . . . 146
UART Modem Status Register . . . . . . . . . . . 147
UART Receiver Buffer Register (when DLAB = 0,
Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . 162
UART Transmitter Holding Register (when
DLAB = 0, Write Only) . . . . . . . . . . . . . . . . . 162
UART Divisor Latch LSB and MSB Registers
(when DLAB = 1) . . . . . . . . . . . . . . . . . . . . . 162
UART Interrupt Enable Register
(when DLAB = 0) . . . . . . . . . . . . . . . . . . . . . 163
UART Interrupt Identification Register . . . . . 164
UART FIFO Control Register . . . . . . . . . . . . 166
DMA operation . . . . . . . . . . . . . . . . . . . . . . . 167
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
8.3.7
8.3.8
8.3.9
8.3.10
8.3.11
8.3.12
8.3.13
8.3.14
9.5.11
9.5.12
9.5.12.1
9.5.12.2
9.5.13
9.5.13.1
9.5.13.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
9.5.13.1.2 Example 2: UART_PCLK = 12 MHz,
9.5.14
9.5.15
9.5.16
9.5.17
9.5.18
9.5.18.1
9.5.18.2
9.5.18.3
9.5.18.4
9.5.18.5
9.5.19
9.6
10.5.7
10.5.8
10.5.9
10.5.10
10.5.10.1 Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 170
10.5.10.2 Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 171
10.5.11
10.5.12
10.5.12.1 Baudrate calculation . . . . . . . . . . . . . . . . . . 175
10.5.12.1.1 Example 1: UART_PCLK = 14.7456 MHz, BR =
10.5.12.1.2 Example 2: UART_PCLK = 12 MHz, BR =
10.5.13
10.5.14
10.6
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 178
GPIO data direction register . . . . . . . . . . . . 134
GPIO interrupt sense register . . . . . . . . . . . 134
GPIO interrupt both edges sense register . . 134
GPIO interrupt event register . . . . . . . . . . . . 134
GPIO interrupt mask register . . . . . . . . . . . . 134
GPIO raw interrupt status register . . . . . . . . 135
GPIO masked interrupt status register. . . . . 135
GPIO interrupt clear register . . . . . . . . . . . . 135
UART Scratch Pad Register . . . . . . . . . . . . 148
UART Auto-baud Control Register . . . . . . . 148
Auto-baud . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Auto-baud modes. . . . . . . . . . . . . . . . . . . . . 150
UART Fractional Divider Register . . . . . . . . 151
Baudrate calculation . . . . . . . . . . . . . . . . . . 152
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
BR = 115200 . . . . . . . . . . . . . . . . . . . . . . . . 154
UART Transmit Enable Register (TER -
0x4000 8030) . . . . . . . . . . . . . . . . . . . . . . . . 154
UART RS485 Control register . . . . . . . . . . . 155
UART RS-485 Address Match register . . . . 156
UART1 RS-485 Delay value register . . . . . 156
RS-485/EIA-485 modes of operation . . . . . . 157
RS-485/EIA-485 Normal Multidrop Mode
(NMM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RS-485/EIA-485 Auto Address Detection (AAD)
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
RS-485/EIA-485 Auto Direction Control. . . . 157
RS485/EIA-485 driver delay time. . . . . . . . . 158
RS485/EIA-485 output inversion . . . . . . . . . 158
UART FIFO Level register . . . . . . . . . . . . . . 158
UART Line Control Register. . . . . . . . . . . . . 167
UART Line Status Register . . . . . . . . . . . . . 168
UART Scratch Pad Register . . . . . . . . . . . . 169
UART Auto-baud Control Register . . . . . . . 170
UART IrDA Control Register . . . . . . . . . . . . 173
UART Fractional Divider Register . . . . . . . . 174
9600 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
115200 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
UART Transmit Enable Register . . . . . . . . . 177
UART FIFO Level register . . . . . . . . . . . . . . 178
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
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