OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 228

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
12.6.6 SSP Interrupt Mask Set/Clear Register (IMSC - 0x4004 0014)
12.6.7 SSP Raw Interrupt Status Register
Table 210. SSP Clock Prescale Register (CPSR - address 0x4004 0010) bit description
Important: the CPSR value must be properly initialized or the SSP controller will not be
able to transmit data correctly.
In Slave mode, the SSP clock rate provided by the master must not exceed 1/12 of the
SSP peripheral clock selected in
relevant.
In master mode, CPSDVSR
This register controls whether each of the four possible interrupt conditions in the SSP
controller are enabled. Note that ARM uses the word “masked” in the opposite sense from
classic computer terminology, in which “masked” meant “disabled”. ARM uses the word
“masked” to mean “enabled”. To avoid confusion we will not use the word “masked”.
Table 211. SSP Interrupt Mask Set/Clear register (IMSC - address 0x4004 0014) bit
This read-only register contains a 1 for each interrupt condition that is asserted,
regardless of whether or not the interrupt is enabled in the IMSC.
Bit
7:0
31:8
Bit
0
1
2
3
31:4
Symbol
CPSDVSR This even value between 2 and 254, by which SSP_PCLK is
-
Symbol
RORIM
RTIM
RXIM
TXIM
-
description
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Description
divided to yield the prescaler output clock. Bit 0 always reads
as 0.
Reserved
Description
Software should set this bit to enable interrupt when a Receive
Overrun occurs, that is, when the Rx FIFO is full and another frame is
completely received. The ARM spec implies that the preceding frame
data is overwritten by the new frame data when this occurs.
Software should set this bit to enable interrupt when a Receive
Time-out condition occurs. A Receive Time-out occurs when the Rx
FIFO is not empty, and no has not been read for a “time-out period”.
The time-out period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR ×
[SCR+1]).
Software should set this bit to enable interrupt when the Rx FIFO is at
least half full.
Software should set this bit to enable interrupt when the Tx FIFO is at
least half empty.
Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
min
= 2 or larger (even numbers only).
Table
22. The content of the CPSR register is not
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
-
228 of 442
Reset
value
0
0
0
0
NA