OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 330

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
21.6.3 Channel control base pointer register
21.6.4 Channel alternate control base pointer register
21.6.5 Channel wait on request status register
21.6.6 Channel software request register
This register is a read/write register and configures the base pointer. The base pointer
must point to a location in the LPC122x’s SRAM because the micro DMA controller
provides no internal memory for storing the channel control data structure.
The register cannot be read when the micro DMA controller is in the reset state.
Table 323. Channel control base pointer register (CTRL_BASE_PTR, address 0x4004 C008)
This register is a read-only register and returns the base address of the alternate data
structure.
This register removes the necessity for application software to calculate the base address
of the alternate data structure (see
The register cannot be read when the micro DMA controller is in the reset state.
Table 324. Channel alternate control base pointer register (ATL_CTRL_BASE_PTR, address
This register is a read-only register and returns the status of the dma_waitonreq[c] signal
for a channel c (c = 0 to 20).
The register cannot be read when the micro DMA controller is in the reset state.
Table 325. Channel wait on request status register (DMA_WAITONREQ_STATUS, address
This is a write-only register and enables the generation of a software DMA request for a
channel c (c = 0 to 20).
Writing to a bit where a DMA channel is not implemented does not create a DMA request
for that channel.
Bit
7:0
31:8
Bit
31:0
Bit
20:0
31:21
Symbol
ALT_CTRL_BASE_PTR
Symbol
DMA_WAITONREQ_
STATUS
-
Symbol
-
CTRL_BASE_PTR
bit description
0x4004 C00C) bit description
0x4004 C010) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 21: LPC122x General purpose micro DMA controller
Description
Reserved. Write as zero.
Pointer to the base address of the primary data structure. 0x0
Description
Channel c wait-on-request status (c = 0 to 20):
Bit c = 0: dma_waitonreq[c] is LOW.
Bit c = 1: dma_waitonreq[c] is HIGH.
Reserved.
Description
Base address of the alternate data structure
Section
21.7.5).
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
-
-
330 of 442
Reset
value
0x0
Reset
value
0x0