OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 151

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
Fig 7.
a. Mode 0 (start bit and LSB are used for auto-baud)
b. Mode 1 (only start bit is used for auto-baud)
16xbaud_rate
16xbaud_rate
U0ACR start
U0ACR start
rate counter
rate counter
UARTn RX
UARTn RX
Auto-baud a) mode 0 and b) mode 1 waveform
9.5.13 UART Fractional Divider Register
The UART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
5. If Mode = 0 then the rate counter will stop on next falling edge of the UART RX pin. If
6. The rate counter is loaded into DLM/DLL and the baud-rate will be switched to normal
Mode = 1 then the rate counter will stop on the next rising edge of the UART RX pin.
operation. After setting the DLM/DLL the end of auto-baud interrupt IIR ABEOInt will
be set, if enabled. The RSR will now continue receiving the remaining bits of the ”A/a"
character.
start
start
16 cycles
16 cycles
bit0
bit0
All information provided in this document is subject to legal disclaimers.
bit1
bit1
start bit
start bit
Rev. 1.1 — 10 March 2011
bit2
bit2
'A' (0x41) or 'a' (0x61)
©A© (0x41) or ©a© (0x61)
bit3
bit3
bit4
bit4
Chapter 9: LPC122x UART0 with modem control
16 cycles
bit5
bit5
bit6
bit6
LSB of 'A' or 'a'
LSB of ©A© or ©a©
bit7
bit7
parity stop
parity stop
UM10441
© NXP B.V. 2011. All rights reserved.
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