OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 413

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.5.2.7.1 Hardware and software control of interrupts
25.5.2.8 NVIC usage hints and tips
rising edge of the processor clock. To ensure the NVIC detects the interrupt, the
peripheral must assert the interrupt signal for at least one clock cycle, during which the
NVIC detects the pulse and latches the interrupt.
When the processor enters the ISR, it automatically removes the pending state from the
interrupt, see
deasserted before the processor returns from the ISR, the interrupt becomes pending
again, and the processor must execute its ISR again. This means that the peripheral can
hold the interrupt signal asserted until it no longer needs servicing.
The Cortex-M0 latches all interrupts. A peripheral interrupt becomes pending for one of
the following reasons:
A pending interrupt remains pending until one of the following:
Ensure software uses correctly aligned register accesses. The processor does not
support unaligned accesses to NVIC registers.
An interrupt can enter pending state even if it is disabled. Disabling an interrupt only
prevents the processor from taking that interrupt.
•
•
•
•
•
the NVIC detects that the interrupt signal is active and the corresponding interrupt is
not active
the NVIC detects a rising edge on the interrupt signal
software writes to the corresponding interrupt set-pending register bit, see
Section
The processor enters the ISR for the interrupt. This changes the state of the interrupt
from pending to active. Then:
– For a level-sensitive interrupt, when the processor returns from the ISR, the NVIC
– For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this
Software writes to the corresponding interrupt clear-pending register bit.
For a level-sensitive interrupt, if the interrupt signal is still asserted, the state of the
interrupt does not change. Otherwise, the state of the interrupt changes to inactive.
For a pulse interrupt, state of the interrupt changes to:
– inactive, if the state was pending
– active, if the state was active and pending.
samples the interrupt signal. If the signal is asserted, the state of the interrupt
changes to pending, which might cause the processor to immediately re-enter the
ISR. Otherwise, the state of the interrupt changes to inactive.
is pulsed the state of the interrupt changes to pending and active. In this case,
when the processor returns from the ISR the state of the interrupt changes to
pending, which might cause the processor to immediately re-enter the ISR.
If the interrupt signal is not pulsed while the processor is in the ISR, when the
processor returns from the ISR the state of the interrupt changes to inactive.
25–25.5.2.4.
Section
All information provided in this document is subject to legal disclaimers.
25.5.2.7.1. For a level-sensitive interrupt, if the signal is not
Rev. 1.1 — 10 March 2011
Chapter 25: LPC122x Appendix ARM Cortex-M0
UM10441
© NXP B.V. 2011. All rights reserved.
413 of 442