OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 135

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
8.3.12 GPIO raw interrupt status register
8.3.13 GPIO masked interrupt status register
8.3.14 GPIO interrupt clear register
Table 132. GPIO interrupt mask register (IE - address 0x5000 0030, 0x5001 0030 (GPIO1),
Bits read HIGH in the IRS register reflect the raw (prior to masking) interrupt status of the
corresponding pins indicating that all the requirements have been met before they are
allowed to trigger the IE. Bits read as zero indicate that the corresponding input pins have
not initiated an interrupt. The register is read-only.
Table 133. GPIO raw interrupt mask status register (RIS - address 0x5000 0034 (GPIO0),
Bits read HIGH in the MIS register reflect the status of the input lines triggering an
interrupt. Bits read as LOW indicate that either no interrupt on the corresponding input
pins has been generated or that the interrupt is masked. MIS is the state of the interrupt
after masking. The register is read-only.
Table 134. GPIO masked interrupt status register (MIS - address 0x5000 0038 (GPIO0),
Remark: The synchronizer between the GPIO and the NVIC blocks causes a delay of 2
clocks. It is recommended to add two NOPs after the clear of the interrupt edge detection
logic, before the exit of the interrupt service routine.
Table 135. GPIO interrupt clear register (IC - address 0x5000 003C, 0x5001 003C (GPIO1),
Bit
31:0
Bit
31:0
Bit
31:0
Bit
31:0
Symbol Description
MASK
Symbol Description
RAWST Raw interrupt status.
Symbol Description
MASK
Symbol
CLR
0x5002 0030 (GPIO2)) bit description
0x5001 0034 (GPIO1), 0x5002 0034 (GPIO2)) bit description
0x5001 0038 (GPIO1), 0x5002 0038 (GPIO2)) bit description
0x5002 003C (GPIO2)) bit description
All information provided in this document is subject to legal disclaimers.
0 = Interrupt on pin PIOn_x is masked.
1 = Interrupt on pin PIOn_x is not masked.
Selects interrupt on pin PIOn_x to be masked.
0 = No interrupt or interrupt masked on pin PIOn_x.
1 = Interrupt on PIOn_x.
Selects interrupt on pin PIOn_x to be masked.
0 = No interrupt on pin PIOn_x.
1 = Interrupt requirements met on PIOn_x.
Description
Selects interrupt on pin PIOn_x to be cleared. Clears the
interrupt edge detection logic.
0 = No effect.
1 = Clears edge detection logic for pin PIOn_x.
Rev. 1.1 — 10 March 2011
Chapter 8: LPC122x General Purpose I/O (GPIO)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0x00
Reset
value
0x00
Reset
value
0x00
Reset
value
0x00
Access
W
Access
R/W
Access
R
Access
R
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