OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 297

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 278. A/D Control Register (CR - address 0x4002 0000) bit description
UM10441
User manual
Bit
7:0
15:8
16
23:17 -
26:24 START
27
31:28 -
Symbol
SEL
CLKDIV
BURST
EDGE
19.6.2 A/D Global Data Register
Value Description
0
1
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
1
0
The A/D Global Data Register contains the result of the most recent A/D conversion. This
includes the data, DONE, and Overrun flags, and the number of the A/D channel to which
the data relates.
Selects which of the AD7:0 pins is (are) to be sampled and converted. For ADC, bit 0
selects Pin AD0, and bit 7 selects pin AD7. In software-controlled mode, only one of these
bits should be 1. In hardware scan mode, any value containing 1 to 8 ones. All zeroes is
equivalent to 0x01.
The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D
converter, which should be less than or equal to 9 MHz. Typically, software should
program the smallest value in this field that yields a clock of 9 MHz or slightly less, but in
certain cases (such as a high-impedance analog source) a slower clock may be
desirable.
Burst mode control.
Conversions are software controlled and require 36 clocks.
The AD converter does repeated conversions up to 250 kHz, scanning (if necessary)
through the pins selected by 1s in the SEL field. The first conversion after the start
corresponds to the least-significant 1 in the SEL field, then higher numbered 1 bits (pins)
if applicable. Repeated conversions can be terminated by clearing this bit, but the
conversion that’s in progress when this bit is cleared will be completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
Reserved. These bits always read as zeros.
Conversion start control. When the BURST bit is 0, these bits control whether and when
an A/D conversion is started.
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on
PIO0_2/SSEL/CT16B0_CAP0.
Start conversion when the edge selected by bit 27 occurs on
PIO1_5/DIR/CT32B0_CAP0.
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0.
Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT1.
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT0.
Start conversion when the edge selected by bit 27 occurs on CT16B0_MAT1.
Edge control. This bit is significant only when the START field contains 010-111.
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved. These bits always read as zeros.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Chapter 19: LPC122x ADC
UM10441
© NXP B.V. 2011. All rights reserved.
297 of 442
Reset
value
0
0
0
0
0
0
0