OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 174

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
10.5.12 UART Fractional Divider Register
Table 174: UART IrDA Control Register (ICR - 0x4000 C024) bit description
The PulseDiv bits in ICR are used to select the pulse width when the fixed pulse width
mode is used in IrDA mode (IrDAEn = 1 and FixPulseEn = 1). The value of these bits
should be set so that the resulting pulse width is at least 1.63 µs.
possible pulse widths.
Table 175: IrDA Pulse Width
The UART Fractional Divider Register (FDR) controls the clock pre-scaler for the baud
rate generation and can be read and written at the user’s discretion. This pre-scaler takes
the APB clock and generates an output clock according to the specified fractional
requirements.
Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater.
Bit
5:3
31:
6
FixPulseEn
0
1
1
1
1
1
1
1
1
PULSEDIV
-
Symbol
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Value
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
-
PulseDiv
x
0
1
2
3
4
5
6
7
Rev. 1.1 — 10 March 2011
Description
Configures the pulse when FixPulseEn = 1.
2 × T
4 × T
8 × T
16 × T
32 × T
64 × T
128 × T
256 × T
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
IrDA Transmitter Pulse width (µs)
3 / (16 × baud rate)
2 × T
4 × T
8 × T
16 × T
32 × T
64 × T
128 × T
256 × T
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
Chapter 10: LPC122x UART1
Table 175
UM10441
© NXP B.V. 2011. All rights reserved.
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