OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 285

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
17.8 Block diagram
UM10441
User manual
17.7.6 Watchdog Timer Warning Interrupt register
17.7.7 Watchdog Timer Window register
The WDWARNINT register determines the watchdog timer counter value that will
generate a watchdog interrupt. When the watchdog timer counter matches the value
defined by WDWARNINT, an interrupt will be generated after the subsequent WDCLK.
A match of the watchdog timer counter to WDWARNINT occurs when the bottom 10 bits
of the counter have the same value as the 10 bits of WARNINT, and the remaining upper
bits of the counter are all 0. This gives a maximum time of 1,023 watchdog timer counts
(4,096 watchdog clocks) for the interrupt to occur prior to a watchdog event. If WARNINT
is set to 0, the interrupt will occur at the same time as the watchdog event.
Table 270. Watchdog Timer Warning Interrupt register (WARNINT - 0x4000 4014) bit
The WDWINDOW register determines the highest WDTV value allowed when a watchdog
feed is performed. If a feed valid sequence completes prior to WDTV reaching the value in
WDWINDOW, a watchdog event will occur.
WDWINDOW resets to the maximum possible WDTV value, so windowing is not in effect.
Values of WDWINDOW below 0x100 will make it impossible to ever feed the watchdog
successfully.
Table 271. Watchdog Timer Window register (WINDOW - 0x4000 4018) bit description
The block diagram of the Watchdog is shown below in the
logic (PCLK - WDCLK) is not shown in the block diagram.
Bit
9:0
31:10
Bit
23:0
31:24
Symbol
WARNINT
-
Symbol
WINDOW
-
description
All information provided in this document is subject to legal disclaimers.
Description
Watchdog warning interrupt compare value.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Watchdog window value.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
Figure
46. The synchronization
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
NA
Reset value
0xFF FFFF
NA
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