OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 380

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.4.3.1 Operands
25.4.3.2 Restrictions when using PC or SP
25.4.3 About the instruction descriptions
Table 364. CMSIS intrinsic functions to generate some Cortex-M0 instructions
The CMSIS also provides a number of functions for accessing the special registers using
MRS and MSR instructions:
Table 365. insic functions to access the special registers
The following sections give more information about using the instructions:
An instruction operand can be an ARM register, a constant, or another instruction-specific
parameter. Instructions act on the operands and often store the result in a destination
register. When there is a destination register in the instruction, it is usually specified before
the other operands.
Many instructions are unable to use, or have restrictions on whether you can use, the
Program Counter (PC) or Stack Pointer (SP) for the operands or destination register.
See instruction descriptions for more information.
Remark: When you update the PC with a BX, BLX, or POP instruction, bit[0] of any
address must be 1 for correct execution. This is because this bit indicates the destination
instruction set, and the Cortex-M0 processor only supports Thumb instructions. When a
BL or BLX instruction writes the value of bit[0] into the LR it is automatically assigned the
value 1.
Instruction
SEV
WFE
WFI
Special register
PRIMASK
CONTROL
MSP
PSP
•
•
•
•
•
•
Section 25.4.3.1 “Operands”
Section 25.4.3.2 “Restrictions when using PC or SP”
Section 25.4.3.3 “Shift Operations”
Section 25.4.3.4 “Address alignment”
Section 25.4.3.5 “PC-relative expressions”
Section 25.4.3.6 “Conditional
All information provided in this document is subject to legal disclaimers.
Access
Read
Write
Read
Write
Read
Write
Read
Write
Rev. 1.1 — 10 March 2011
execution”.
CMSIS function
uint32_t __get_PRIMASK (void)
void __set_PRIMASK (uint32_t value)
uint32_t __get_CONTROL (void)
void __set_CONTROL (uint32_t value)
uint32_t __get_MSP (void)
void __set_MSP (uint32_t TopOfMainStack)
uint32_t __get_PSP (void)
void __set_PSP (uint32_t TopOfProcStack)
Chapter 25: LPC122x Appendix ARM Cortex-M0
CMSIS intrinsic function
void __SEV(void)
void __WFE(void)
void __WFI(void)
UM10441
© NXP B.V. 2011. All rights reserved.
380 of 442