OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 381

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
Fig 68. ASR #3
31
25.4.3.3.1 ASR
25.4.3.3.2 LSR
25.4.3.3 Shift Operations
Register shift operations move the bits in a register left or right by a specified number of
bits, the shift length. Register shift can be performed directly by the instructions ASR,
LSR, LSL, and ROR and the result is written to a destination register.The permitted shift
lengths depend on the shift type and the instruction, see the individual instruction
description. If the shift length is 0, no shift occurs. Register shift operations update the
carry flag except when the specified shift length is 0. The following sub-sections describe
the various shift operations and how they affect the carry flag. In these descriptions, Rm is
the register containing the value to be shifted, and n is the shift length.
Arithmetic shift right by n bits moves the left-hand 32 -n bits of the register Rm, to the right
by n places, into the right-hand 32 -n bits of the result, and it copies the original bit[31] of
the register into the left-hand n bits of the result. See
You can use the ASR operation to divide the signed value in the register Rm by 2
the result being rounded towards negative-infinity.
When the instruction is ASRS the carry flag is updated to the last bit shifted out, bit[n-1], of
the register Rm.
Remark:
Logical shift right by n bits moves the left-hand 32-n bits of the register Rm, to the right by
n places, into the right-hand 32 -n bits of the result, and it sets the left-hand n bits of the
result to 0. See
You can use the LSR operation to divide the value in the register Rm by 2
regarded as an unsigned integer.
When the instruction is LSRS, the carry flag is updated to the last bit shifted out, bit[n-1],
of the register Rm.
Remark:
•
•
If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
All information provided in this document is subject to legal disclaimers.
Figure
Rev. 1.1 — 10 March 2011
69.
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Chapter 25: LPC122x Appendix ARM Cortex-M0
Figure
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25–68.
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UM10441
© NXP B.V. 2011. All rights reserved.
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Carry
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