OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 164

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
10.5.5 UART Interrupt Identification Register
Table 166. UART Interrupt Enable Register (IER - address 0x4000 C004 when DLAB = 0) bit
The IIR provides a status code that denotes the priority and source of a pending interrupt.
The interrupts are frozen during an IIR access. If an interrupt occurs during an IIR access,
the interrupt is recorded for the next IIR access.
Table 167. UART Interrupt Identification Register (IIR - address 0x4004 C008, Read Only) bit
Bit IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
Bit
9
31:10 -
Bit
0
3:1
5:4
7:6
8
9
31:10 -
Symbol
ABTOINTEN
INTID
-
FIFOEN
ABEOINT
ABTOINT
Symbol
INTSTATUS
description
description
All information provided in this document is subject to legal disclaimers.
Value Description
0
0x3
0x2
0x6
0x1
Rev. 1.1 — 10 March 2011
Value
…continued
1
0
1
Interrupt status. Note that IIR[0] is active low. The pending
interrupt can be determined by evaluating IIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. IER[3:1] identifies an interrupt
corresponding to the UART RX FIFO. All other
combinations of IER[3:1] not listed below are reserved
(000,100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
FIFO enable. These bits are equivalent to FCR[0].
End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
Enables the auto-baud time-out interrupt.
Disable auto-baud time-out Interrupt.
Enable auto-baud time-out Interrupt.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is
not defined.
Table
168. Given the status of IIR[3:0], an interrupt
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
164 of 442
Reset
value
0
NA
Reset
value
1
0
NA
0
0
0
NA