OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 140

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
9.5.5 UART Interrupt Identification Register
The IIR provides a status code that denotes the priority and source of a pending interrupt.
The interrupts are frozen during an IIR access. If an interrupt occurs during an IIR access,
the interrupt is recorded for the next IIR access.
Table 143. UART Interrupt Identification Register (IIR - address 0x4004 8008, Read Only) bit
Bit IIR[9:8] are set by the auto-baud function and signal a time-out or end of auto-baud
condition. The auto-baud interrupt conditions are cleared by setting the corresponding
Clear bits in the Auto-baud Control Register.
If the IntStatus bit is 1 no interrupt is pending and the IntId bits will be zero. If the IntStatus
is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the type of
interrupt and handling as described in
handler routine can determine the cause of the interrupt and how to clear the active
interrupt. The IIR must be read in order to clear the interrupt prior to exiting the Interrupt
Service Routine.
The UART RLS interrupt (IIR[3:1] = 011) is the highest priority interrupt and is set
whenever any one of four error conditions occur on the UART RX input: overrun error
(OE), parity error (PE), framing error (FE) and break interrupt (BI). The UART RX error
condition that set the interrupt can be observed via LSR[4:1]. The interrupt is cleared upon
an LSR read.
Bit
0
3:1
5:4
7:6
8
9
31:10 -
INTID
-
FIFOENA
ABEOINT
ABTOINT
Symbol
INTSTATUS
description
All information provided in this document is subject to legal disclaimers.
Value Description
0x3
0x2
0x6
0x1
0x0
Rev. 1.1 — 10 March 2011
0
1
Interrupt status. Note that IIR[0] is active low. The pending
interrupt can be determined by evaluating IIR[3:1].
At least one interrupt is pending.
No interrupt is pending.
Interrupt identification. IER[3:1] identifies an interrupt
corresponding to the UART RX FIFO. All other
combinations of IER[3:1] not listed below are reserved
(100,101,111).
1 - Receive Line Status (RLS).
2a - Receive Data Available (RDA).
2b - Character Time-out Indicator (CTI).
3 - THRE Interrupt.
4 - Modem interrupt.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
These bits are equivalent to FCR[0].
End of auto-baud interrupt. True if auto-baud has finished
successfully and interrupt is enabled.
Auto-baud time-out interrupt. True if auto-baud has timed
out and interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Chapter 9: LPC122x UART0 with modem control
Table
144. Given the status of IIR[3:0], an interrupt
UM10441
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Reset
value
1
0
NA
0
0
0
NA