OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 168

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
10.5.8 UART Line Status Register
Table 170. UART Line Control Register (LCR - address 0x4000 C00C) bit description
The LSR is a Read Only register that provides status information on the UART TX and RX
blocks.
Table 171. UART Line Status Register (LSR - address 0x4000 C014, Read Only) bit
Bit
5:4
6
7
31:
8
Bit Symbol
0
1
2
RDR
OE
PE
Symbol Value Description
PS
BC
DLAB
-
description
0x0
0x1
0x2
0x3
0
1
0
1
-
All information provided in this document is subject to legal disclaimers.
Value Description
0
1
0
1
0
1
Parity Select
Odd parity. Number of 1s in the transmitted character and the
attached parity bit will be odd.
Even Parity. Number of 1s in the transmitted character and the
attached parity bit will be even.
Forced 1 stick parity.
Forced 0 stick parity.
Break Control
Disable break transmission.
Enable break transmission. Output pin UART TXD is forced to logic
0 when LCR[6] is active high.
Divisor Latch Access Bit (DLAB)
Disable access to Divisor Latches.
Enable access to Divisor Latches.
Reserved
Rev. 1.1 — 10 March 2011
Receiver Data Ready. LSR[0] is set when the RBR holds an
unread character and is cleared when the UART RBR FIFO is
empty.
RBR is empty.
RBR contains valid data.
Overrun Error. The overrun error condition is set as soon as it
occurs. An LSR read clears LSR[1]. LSR[1] is set when UART
RSR has a new character assembled and the UART RBR FIFO is
full. In this case, the UART RBR FIFO will not be overwritten and
the character in the UART RSR will be lost.
Overrun error status is inactive.
Overrun error status is active.
Parity Error. When the parity bit of a received character is in the
wrong state, a parity error occurs. An LSR read clears LSR[2].
Time of parity error detection is dependent on FCR[0].
Note: A parity error is associated with the character at the top of
the UART RBR FIFO.
Parity error status is inactive.
Parity error status is active.
Chapter 10: LPC122x UART1
UM10441
© NXP B.V. 2011. All rights reserved.
168 of 442
Reset
value
0
0
-
Reset
value
0
0
0
0