OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 141

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
The UART RDA interrupt (IIR[3:1] = 010) shares the second level priority with the CTI
interrupt (IIR[3:1] = 110). The RDA is activated when the UART RX FIFO reaches the
trigger level defined in FCR7:6 and is reset when the UART RX FIFO depth falls below the
trigger level. When the RDA interrupt goes active, the CPU can read a block of data
defined by the trigger level.
The CTI interrupt (IIR[3:1] = 110) is a second level interrupt and is set when the UART RX
FIFO contains at least one character and no UART RX FIFO activity has occurred in 3.5 to
4.5 character times. Any UART RX FIFO activity (read or write of UART RSR) will clear
the interrupt. This interrupt is intended to flush the UART RBR after a message has been
received that is not a multiple of the trigger level size. For example, if a peripheral wished
to send a 105 character message and the trigger level was 10 characters, the CPU would
receive 10 RDA interrupts resulting in the transfer of 100 characters and 1 to 5 CTI
interrupts (depending on the service routine) resulting in the transfer of the remaining 5
characters.
Table 144. UART Interrupt Handling
[1]
[2]
[3]
[4]
The UART THRE interrupt (IIR[3:1] = 001) is a third level interrupt and is activated when
the UART THR FIFO is empty provided certain initialization conditions have been met.
These initialization conditions are intended to give the UART THR FIFO a chance to fill up
with data to eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit whenever
THRE = 1 and there have not been at least two characters in the THR at one time since
IIR[3:0]
value
0001
0110
0100
1100
0010
Values "0000", “0011”, “0101”, “0111”, “1000”, “1001”, “1010”, “1011”,”1101”,”1110”,”1111” are reserved.
For details see
For details see
For details see
Holding Register (when DLAB = 0, Write Only)”
[1]
Priority Interrupt
-
Highest RX Line
Second RX Data
Second Character
Third
All information provided in this document is subject to legal disclaimers.
Section 9.5.9 “UART Line Status Register”
Section 9.5.1 “UART Receiver Buffer Register (when DLAB = 0, Read Only)”
Section 9.5.5 “UART Interrupt Identification Register”
type
None
Status /
Error
Available
Time-out
indication
THRE
Rev. 1.1 — 10 March 2011
Interrupt source
None
OE
RX data available or trigger level reached in FIFO
(FCR0=1)
Minimum of one character in the RX FIFO and no
character input or removed during a time period
depending on how many characters are in FIFO
and what the trigger level is set at (3.5 to 4.5
character times).
The exact time will be:
[(word length) × 7 - 2] × 8 + [(trigger level - number
of characters) × 8 + 1] RCLKs
THRE
[2]
or PE
[2]
Chapter 9: LPC122x UART0 with modem control
[2]
or FE
[2]
or BI
[2]
and
Section 9.5.2 “UART Transmitter
UM10441
© NXP B.V. 2011. All rights reserved.
Interrupt
reset
-
LSR Read
RBR
Read
UART FIFO
drops below
trigger level
RBR
Read
IIR Read
(if source of
interrupt) or
THR write
141 of 442
[3]
[3]
or
[4]
[2]