OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 242

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 220. Interrupt Register (IR, address 0x4001 0000 (CT16B0) and 0x4001 4000 (CT16B1)) bit description
UM10441
User manual
Bit
0
1
2
3
4
5
6
7
31:8
Symbol
MR0INT
MR1INT
MR2INT
MR3INT
CR0INT
CR1INT
CR2INT
CR3INT
-
13.7.1 Interrupt Register
13.7.2 Timer Control Register
13.7.3 Timer Counter
The Interrupt Register consists of four bits for the match interrupts and two bits for the
capture interrupts. If an interrupt is generated then the corresponding bit in the IR will be
HIGH. Otherwise, the bit will be LOW. Writing a logic one to the corresponding IR bit will
reset the interrupt. Writing a zero has no effect. Clearing an interrupt for timer match also
clears any corresponding DMA request.
The Timer Control Register (TCR) is used to control the operation of the counter/timer.
Table 221. Timer Control Register (TCR, address 0x4001 0004 (CT16B0) and 0x4001 4004
The 16-bit Timer Counter is incremented when the Prescale Counter reaches its terminal
count. Unless it is reset before reaching its upper limit, the TC will count up to the value
0x0000 FFFF and then wrap back to the value 0x0000 0000. This event does not cause
an interrupt, but a Match register can be used to detect an overflow if needed.
Bit
0
1
31:
2
Symbol Value
CEN
CRST
-
Description
Interrupt flag for match channel 0.
Interrupt flag for match channel 1.
Interrupt flag for match channel 2.
Interrupt flag for match channel 3.
Interrupt flag for capture channel 0 event.
Interrupt flag for capture channel 1 event.
Interrupt flag for capture channel 2 event.
Interrupt flag for capture channel 3 event.
Reserved
(CT16B1)) bit description
0
1
0
1
All information provided in this document is subject to legal disclaimers.
Description
Counter enable.
The counters are disabled.
The Timer Counter and Prescale Counter are enabled for
counting.
Counter reset.
Do nothing.
The Timer Counter and the Prescale Counter are
synchronously reset on the next positive edge of PCLK. The
counters remain reset until TCR[1] is returned to zero.
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 13: LPC122x 16-bit Counter/timer 0/1 (CT16B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
0
0
0
0
0
-
Reset
value
0
0
NA
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