OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 360

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
25.3.1.3.3 Link Register
25.3.1.3.4 Program Counter
25.3.1.3.5 Program Status Register
On reset, the processor loads the MSP with the value from address 0x00000000.
The Link Register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions. On reset, the LR value is Unknown.
The Program Counter (PC) is register R15. It contains the current program address. On
reset, the processor loads the PC with the value of the reset vector, which is at address
0x00000004. Bit[0] of the value is loaded into the EPSR T-bit at reset and must be 1.
The Program Status Register (PSR) combines:
These registers are mutually exclusive bitfields in the 32-bit PSR. The PSR bit
assignments are:
Access these registers individually or as a combination of any two or all three registers,
using the register name as an argument to the MSR or MRS instructions. For example:
The PSR combinations and attributes are:
Table 354. PSR register combinations
[1]
[2]
Register
PSR
IEPSR
IAPSR
EAPSR
APSR
EPSR
Fig 62. APSR, IPSR, EPSR register bit assignments
•
•
•
•
•
IPSR
Application Program Status Register (APSR)
Interrupt Program Status Register (IPSR)
Execution Program Status Register (EPSR).
read all of the registers using PSR with the MRS instruction
write to the APSR using APSR with the MSR instruction.
The processor ignores writes to the IPSR bits.
Reads of the EPSR bits return zero, and the processor ignores writes to the these bits
31 30 29 28 27
N Z C V
Reserved
All information provided in this document is subject to legal disclaimers.
Type
RW
RO
RW
RW
[1][2]
[1]
[2]
Rev. 1.1 — 10 March 2011
25 24 23
T
Combination
APSR, EPSR, and IPSR
EPSR and IPSR
APSR and IPSR
APSR and EPSR
Reserved
Chapter 25: LPC122x Appendix ARM Cortex-M0
Reserved
Reserved
UM10441
© NXP B.V. 2011. All rights reserved.
6
Exception number
5
360 of 442
0