OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 255

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
14.5 General description
14.6 Pin description
Table 233. Counter/timer pin description
14.7 Register description
Table 234. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 8000)
UM10441
User manual
Pin
CT32B0_CAP[3:0]
CT32B1_CAP[3:0]
CT32B0_MAT[3:0]
CT32B1_MAT[3:0]
Name
IR
TCR
TC
PR
Access Address
R/W
R/W
R/W
R/W
Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an
externally supplied clock and can optionally generate interrupts or perform other actions at
specified timer values based on four match registers. Each counter/timer also includes
one capture input to trap the timer value when an input signal transitions, optionally
generating an interrupt.
In PWM mode, three match registers can be used to provide a single-edge controlled
PWM output on the match output pins. One match register is used to control the PWM
cycle length.
Remark: 32-bit counter/timer0 (CT32B0) and 32-bit counter/timer1 (CT32B1) are
functionally identical except for their peripheral base addresses.
Table 233
32-bit counter/timer0 contains the registers shown in
contains the registers shown in
Type
Input
Output
offset
0x000
0x004
0x008
0x00C
gives a brief summary of each of the counter/timer related pins.
Description
Capture Signals:
A transition on a capture pin can be configured to load one of the Capture Registers
with the value in the Timer Counter and optionally generate an interrupt.
The counter/timer block can select a capture signal as a clock source instead of the
PCLK derived clock. For more details see
page
External Match Output of CT32B0/1:
When a match register MR3:0 equals the timer counter (TC), this output can either
toggle, go LOW, go HIGH, or do nothing. The External Match Register (EMR) and the
PWM Control register (PWMCON) control the functionality of this output.
Description
Interrupt Register. The IR can be written to clear interrupts. The IR can
be read to identify which of eight possible interrupt sources are pending.
Timer Control Register. The TCR is used to control the Timer Counter
functions. The Timer Counter can be disabled or reset through the TCR.
Timer Counter. The 32-bit TC is incremented every PR+1 cycles of
PCLK. The TC is controlled through the TCR.
Prescale Register. When the Prescale Counter (below) is equal to this
value, the next clock increments the TC and clears the PC.
All information provided in this document is subject to legal disclaimers.
264.
Rev. 1.1 — 10 March 2011
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
Table
235. More detailed descriptions follow.
Section 14.7.11 “Count Control Register” on
Table 234
and 32-bit counter/timer1
UM10441
© NXP B.V. 2011. All rights reserved.
Reset
value
0
0
0
0
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