OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 432

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
26.5 Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10. Auto-baud a) mode 0 and b) mode 1 waveform 173
Fig 11. Algorithm for setting UART dividers. . . . . . . . . .176
Fig 12. UART1 block diagram . . . . . . . . . . . . . . . . . . . .179
Fig 13. I
Fig 14. Format in the Master Transmitter mode. . . . . . .191
Fig 15. Format of Master Receiver mode . . . . . . . . . . .192
Fig 16. A Master Receiver switches to Master Transmitter
Fig 17. Format of Slave Receiver mode . . . . . . . . . . . .193
Fig 18. Format of Slave Transmitter mode . . . . . . . . . .194
Fig 19. I
Fig 20. Arbitration procedure . . . . . . . . . . . . . . . . . . . . .197
Fig 21. Serial clock synchronization. . . . . . . . . . . . . . . .197
Fig 22. Format and states in the Master Transmitter
Fig 23. Format and states in the Master Receiver
Fig 24. Format and states in the Slave Receiver mode .205
Fig 25. Format and states in the Slave Transmitter
Fig 26. Simultaneous repeated START conditions from two
Fig 27. Forced access to a busy I
Fig 28. Recovering from a bus obstruction caused by a
Fig 29. Texas Instruments Synchronous Serial Frame
Fig 30. SPI frame format with CPOL=0 and CPHA=0 (a)
Fig 31. SPI frame format with CPOL=0 and CPHA=1 . .233
Fig 32. SPI frame format with CPOL = 1 and CPHA = 0 (a)
Fig 33. SPI Frame Format with CPOL = 1 and
Fig 34. Microwire frame format (single transfer) . . . . . .236
Fig 35. Microwire frame format (continuos transfers) . .237
Fig 36. Microwire frame format setup and hold details .237
Fig 37. Sample PWM waveforms with a PWM cycle length
Fig 38. A timer cycle in which PR=2, MRx=6, and both
Fig 39. A timer cycle in which PR=2, MRx=6, and both
Fig 40. 16-bit counter/timer block diagram. . . . . . . . . . .253
Fig 41. Sample PWM waveforms with a PWM cycle length
UM10441
User manual
LPC122x block diagram. . . . . . . . . . . . . . . . . . . . .6
LPC122x memory map . . . . . . . . . . . . . . . . . . . . .8
LPC122x CGU block diagram . . . . . . . . . . . . . . .12
System PLL block diagram . . . . . . . . . . . . . . . . .52
Auto-RTS Functional Timing . . . . . . . . . . . . . . .145
Auto-CTS Functional Timing . . . . . . . . . . . . . . .146
Auto-baud a) mode 0 and b) mode 1 waveform 151
Algorithm for setting UART dividers. . . . . . . . . .153
UART block diagram . . . . . . . . . . . . . . . . . . . . .159
after sending repeated START . . . . . . . . . . . . .192
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203
mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206
masters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213
LOW level on SDA . . . . . . . . . . . . . . . . . . . . . . .214
Format: a) Single and b) Continuous/back-to-back
Two Frames Transfer. . . . . . . . . . . . . . . . . . . . .231
Single and b) Continuous Transfer) . . . . . . . . . .232
Single and b) Continuous Transfer) . . . . . . . . . .234
CPHA = 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . .252
interrupt and reset on match are enabled . . . . .252
interrupt and stop on match are enabled . . . . . .252
2
2
C-bus configuration . . . . . . . . . . . . . . . . . . . . .181
C serial interface block diagram . . . . . . . . . . .195
2
C-bus. . . . . . . . . . . .214
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Fig 42. A timer cycle in which PR=2, MRx=6, and both
Fig 43. A timer cycle in which PR=2, MRx=6, and both
Fig 44. 32-bit counter/timer block diagram . . . . . . . . . . 269
Fig 45. System tick timer block diagram . . . . . . . . . . . . 270
Fig 46. Watchdog block diagram. . . . . . . . . . . . . . . . . . 286
Fig 47. Early Watchdog Feed with Windowed Mode
Fig 48. Correct Watchdog Feed with Windowed Mode
Fig 49. Watchdog Warning Interrupt . . . . . . . . . . . . . . . 287
Fig 50. Comparator block diagram . . . . . . . . . . . . . . . . 292
Fig 51. Comparator inputs. . . . . . . . . . . . . . . . . . . . . . . 293
Fig 52. Memory map of flash and boot ROM memory
Fig 53. Boot process flowchart . . . . . . . . . . . . . . . . . . . 305
Fig 54. IAP parameter passing . . . . . . . . . . . . . . . . . . . 319
Fig 55. Micro DMA controller block diagram . . . . . . . . . 326
Fig 56. DMA ping-pong cycle . . . . . . . . . . . . . . . . . . . . 342
Fig 57. Memory map for the micro DMA channel control
Fig 58. CRC block diagram . . . . . . . . . . . . . . . . . . . . . . 349
Fig 59. Connecting the SWD pins to a standard SWD
Fig 60. Cortex-M0 implementation . . . . . . . . . . . . . . . . 356
Fig 61. Processor core register set . . . . . . . . . . . . . . . . 359
Fig 62. APSR, IPSR, EPSR register bit assignments . 360
Fig 63. Cortex-M0 memory map . . . . . . . . . . . . . . . . . . 365
Fig 64. Memory ordering restrictions. . . . . . . . . . . . . . . 366
Fig 65. Little-endian format . . . . . . . . . . . . . . . . . . . . . . 368
Fig 66. Vector table . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371
Fig 67. Exeption entry stack contents . . . . . . . . . . . . . . 373
Fig 68. ASR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381
Fig 69. LSR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Fig 70. LSL #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382
Fig 71. ROR #3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383
Fig 72. IPR register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412
of 100 (selected by MR3) and MAT3:0 enabled as
PWM outputs by the PWCON register. . . . . . . . 267
interrupt and reset on match are enabled . . . . . 268
interrupt and stop on match are enabled . . . . . 268
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
Enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
data structure (8 channels) . . . . . . . . . . . . . . . . 343
connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355
Chapter 26: Supplementary information
UM10441
© NXP B.V. 2011. All rights reserved.
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