OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 130

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

8.1 How to read this chapter
8.2 Introduction
8.3 Register description
UM10441
User manual
8.2.1 Features
Each pin has one bit in one of the GPIO registers assigned. GPIO registers for pins not
available are reserved (see
packages.
Table 120. Available GPIO pins/ports
Each GPIO register is 32-bit wide. The MASK register masks all operations on the PIN,
OUT, SET, CLR, and NOT registers. The registers DIR to IC are not affected by the bits
set in the MASK register.
Each bit in the GPIO registers represents one GPIO pin. The pin configuration for each
port determines which pins are used or reserved:
Port
GPIO0
GPIO1
GPIO2
•
•
•
•
•
•
•
•
•
•
•
UM10441
Chapter 8: LPC122x General Purpose I/O (GPIO)
Rev. 1.1 — 10 March 2011
Digital ports can be configured as input or output by software.
Read and write data operations from/to the port pins are maskable.
Bit-level set and clear registers allow a single-instruction set or clear of any number of
pins in one port.
Bit-level invert registers allow inverting the output of any number of pins in one port.
Each individual port pin can serve as external interrupt input.
Interrupts can be configured on single falling or rising edges and on both edges.
Individual interrupt levels can be programmed.
All GPIO pins are configured as inputs (with pull-up resistors enabled, see
Section
Port 0: All GPIO0 registers use bits 0 to 31.
Port 1: All GPIO1 registers use bits 0 to 6. Bits 7 to 31 are reserved.
Port 2: All GPIO2 registers use bits 0 to 15. Bits 16 to 31 are reserved.
Pins
PIO0_0 to PIO0_31
PIO1_0 to PIO1_6
PIO2_0 to PIO2_15
6.3.2) after reset.
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table
120). GPIO port 2 registers are only available on 64-pin
6:0
15:0
GPIO register bits used
31:0
LQFP48
yes
yes
no
© NXP B.V. 2011. All rights reserved.
LQFP64
yes
yes
yes
User manual
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