OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 198

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
11.9.10 Status decoder and status register
11.9.8 Timing and control
11.9.9 Control register, CONSET and CONCLR
via the I
registers for details. The output clock pulses have a duty cycle as programmed unless the
bus is synchronizing with other SCL clock sources as described above.
The timing and control logic generates the timing and control signals for serial byte
handling. This logic block provides the shift pulses for DAT, enables the comparator,
generates and detects START and STOP conditions, receives and transmits acknowledge
bits, controls the master and slave modes, contains interrupt request logic, and monitors
the I
The I
and restart of a serial transfer, termination of a serial transfer, bit rate, address recognition,
and acknowledgment.
The contents of the I
set bits in the I
writing to CONCLR will clear bits in the I
value written.
The status decoder takes all of the internal status bits and compresses them into a 5-bit
code. This code is unique for each I
generate vector addresses for fast processing of the various service routines. Each
service routine processes a particular bus status. There are 26 possible bus states if all
four modes of the I
significant bits of the status register when the serial interrupt flag is set (by hardware) and
remains stable until the interrupt flag is cleared by software. The three least significant bits
of the status register are always zero. If the status code is used as a vector to service
routines, then the routines are displaced by eight address locations. Eight bytes of code is
sufficient for most of the service routines (see the software example in this section).
2
2
C-bus status.
C control register contains bits used to control the following I
2
C Clock Control Registers. See the description of the CSCLL and CSCLH
2
C control register that correspond to ones in the value written. Conversely,
All information provided in this document is subject to legal disclaimers.
2
C block are used. The 5-bit status code is latched into the five most
2
C control register may be read as CONSET. Writing to CONSET will
Rev. 1.1 — 10 March 2011
2
C-bus status. The 5-bit code may be used to
2
C control register that correspond to ones in the
Chapter 11: LPC122x I2C-bus controller
2
C block functions: start
UM10441
© NXP B.V. 2011. All rights reserved.
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