OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 282

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 264. Watchdog Mode register (MOD - 0x4000 4000) bit description
UM10441
User manual
Bit
5
6
7
31:
8
Symbol
WDLOCKCLK
WDLOCKDP
WDLOCKEN
-
Value
0
1
0
1
0
1
Description
Watchdog clock lock bit.
This bit is cleared on reset and can subsequently be written to only once to
set it. Once this bit has been set, it can only be cleared through resetting the
chip.
The watchdog clock (WDCLK) can be disabled at any time.
Setting this bit disables any writes to the bit or bits that control the power to
the currently selected watchdog clock source in the power configuration
registers PDRUNCFG, PDSLEEPCFG, and PDAWAKECFG. Other bits in
the power configuration registers are not affected. Setting the WDLOCKCLK
bit ensures that the WDT always has a valid clock source for WDCLK
provided that the watchdog oscillator and/or the IRC are powered.
Remark: Before setting the WDLOCKCLK bit, the user must enable either
the watchdog oscillator or the IRC or both in all three power configuration
registers in order to keep the selected clock source running in Active, Sleep,
or Deep-sleep modes. Once the WDLOCKCLK bit is set, the watchdog clock
source cannot be switched off or on. If the WDT is to be running in
Deep-sleep mode, the watchdog oscillator must be enabled in the
PDSLEEPCFG register before setting the WDLOCKCLK bit (see
Table 48 “Deep-sleep configuration register (PDSLEEPCFG, address
0x4004 8230) bit
Deep power-down disable bit. This bit is cleared on reset and can
subsequently be written to only once to set it. Once this bit has been set, it
can only be cleared through resetting the chip.
Deep power-down mode can be entered at any time.
The DPDEN bit in the PMU (see
address 0x4003 8000) bit
Watchdog enable and reset lockout bit. This bit is cleared on reset and can
subsequently be written to only once to set it. Once this bit has been set, it
can only be cleared through resetting the chip.
The WDEN and WDRESET bits can be written to by software any time to
enable or disable watchdog operation.
If this bit is set to one, all subsequent writes to the WDEN and WDRESET
bits will be blocked. The watchdog will be permanently disabled or enabled
depending on the state of the WDEN bit when the WDLOCK bit was set. The
reset behavior is affected as follows:
Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
•
•
If the watchdog is enabled and the WDRESET is bit set to one before
setting the WDLOCKEN bit, a watchdog trigger always causes a reset
and this behavior cannot be overwritten by software.
If the watchdog is enabled and the WDRESET bit is set to zero before
setting the WDLOCKEN bit, a watchdog trigger always causes an
interrupt and this behavior cannot be overwritten by software.
All information provided in this document is subject to legal disclaimers.
description”).
Rev. 1.1 — 10 March 2011
Chapter 17: LPC122x Windowed Watchdog Timer (WWDT)
description”) cannot be set to 1.
Table 56 “Power control register (PCON,
…continued
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
-
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