OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 431

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 332. Channel enable clear register
Table 333. Channel primary-alternate set register
Table 334. Channel primary-alternate clear register
Table 335. Channel priority set register
Table 336. Channel priority clear register
Table 337. Bus error clear register (ERR_CLR, address
Table 338. Channel DMA interrupt status register
Table 339. DMA error interrupt enable register
Table 340. Channel DMA interrupt enable register
Table 341. DMA control signals . . . . . . . . . . . . . . . . . . . .338
Table 342. DMA channel priority . . . . . . . . . . . . . . . . . . .340
Table 343. src_data_end_ptr bit assignments . . . . . . . . .343
Table 344. dst_data_end_ptr bit assignments . . . . . . . . .344
Table 345. channel_cfg bit assignments . . . . . . . . . . . .345
Table 346. Register overview: CRC engine (base address
Table 347. CRC mode register (MODE, address 0x5007
Table 348. CRC seed register (SEED, address 0x5007
Table 349. CRC checksum register (SUM, address 0x5007
Table 350. CRC data register (WR_DATA, address 0x5007
Table 351. Serial Wire Debug pin description . . . . . . . . .354
Table 352. Summary of processor mode and stack use
Table 353. Core register set summary. . . . . . . . . . . . . . .359
Table 354. PSR register combinations . . . . . . . . . . . . . .360
Table 355. APSR bit assignments . . . . . . . . . . . . . . . . . .361
Table 356. IPSR bit assignments. . . . . . . . . . . . . . . . . . .361
Table 357. EPSR bit assignments . . . . . . . . . . . . . . . . . .362
Table 358. PRIMASK register bit assignments . . . . . . . .362
Table 359. CONTROL register bit assignments . . . . . . .363
Table 360. Memory access behavior . . . . . . . . . . . . . . . .367
Table 361. Properties of different exception types. . . . . .369
Table 362. Exeption return behavior . . . . . . . . . . . . . . . .374
Table 363. Cortex-M0 instructions . . . . . . . . . . . . . . . . . .377
Table 364. CMSIS intrinsic functions to generate some
UM10441
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . . .333
(CHNL_ENABLE_CLR, address 0x4004 C02C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .334
(CHNL_PRI_ALT_SET, address 0x4004 C030) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .334
(CHNL_PRI_ALT_CLR, address 0x4004 C034)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .335
(CHNL_PRIORITY_SET, address 0x4004 C038)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .336
(CHNL_PRIORITY_CLR, address 0x4004 C03C)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .336
0x4004 C04C) bit description . . . . . . . . . . . . .337
(CHNL_IRQ_STATUS, address 0x4004 C080) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .337
(IRQ_ERR_ENABLE, address 0x4004 C084) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .337
(CHNL_IRQ_ENABLE, address 0x4004 C088) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .338
0x5007 0000) . . . . . . . . . . . . . . . . . . . . . . . . .349
0000) bit description . . . . . . . . . . . . . . . . . . . .350
0004) bit description . . . . . . . . . . . . . . . . . . . .350
0008) bit description . . . . . . . . . . . . . . . . . . . .350
0008) bit description . . . . . . . . . . . . . . . . . . . .351
options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .358
Cortex-M0 instructions . . . . . . . . . . . . . . . . . .379
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Table 365. insic functions to access the special
Table 366. Condition code suffixes . . . . . . . . . . . . . . . . . 384
Table 367. Access instructions . . . . . . . . . . . . . . . . . . . 385
Table 368. Data processing instructions . . . . . . . . . . . . . 391
Table 369. ADC, ADD, RSB, SBC and SUB operand
Table 370. Branch and control instructions. . . . . . . . . . . 400
Table 371. Branch ranges. . . . . . . . . . . . . . . . . . . . . . . . 401
Table 372. Miscellaneous instructions . . . . . . . . . . . . . . 402
Table 373. Core peripheral register regions . . . . . . . . . . 409
Table 374. NVIC register summary. . . . . . . . . . . . . . . . . 409
Table 375. CMISIS acess NVIC functions
Table 376. ISER bit assignments . . . . . . . . . . . . . . . . . . 410
Table 377. ICER bit assignments . . . . . . . . . . . . . . . . . . 411
Table 378. ISPR bit assignments . . . . . . . . . . . . . . . . . . 411
Table 379. ICPR bit assignments . . . . . . . . . . . . . . . . . . 411
Table 380. IPR bit assignments . . . . . . . . . . . . . . . . . . . 412
Table 381. CMSIS functions for NVIC control. . . . . . . . . 414
Table 382. Summary of the SCB registers . . . . . . . . . . . 414
Table 383. CPUID register bit assignments . . . . . . . . . . 415
Table 384. ICSR bit assignments . . . . . . . . . . . . . . . . . . 416
Table 385. AIRCR bit assignments . . . . . . . . . . . . . . . . . 417
Table 386. SCR bit assignments. . . . . . . . . . . . . . . . . . . 418
Table 387. CCR bit assignments . . . . . . . . . . . . . . . . . . 419
Table 388. System fault handler priority fields . . . . . . . . 419
Table 389. SHPR2 register bit assignments . . . . . . . . . . 419
Table 390. SHPR3 register bit assignments . . . . . . . . . . 420
Table 391. System timer registers summary. . . . . . . . . . 420
Table 392. SYST_CSR bit assignments . . . . . . . . . . . . . 420
Table 393. SYST_RVR bit assignments . . . . . . . . . . . . . 421
Table 394. SYST_CVR bit assignments . . . . . . . . . . . . . 421
Table 395. SYST_CALIB register bit assignments . . . . . 422
Table 396. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . 423
registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380
restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Chapter 26: Supplementary information
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© NXP B.V. 2011. All rights reserved.
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