OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 229

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
UM10441
User manual
12.6.8 SSP Masked Interrupt Status Register
12.6.9 SSP Interrupt Clear Register
Table 212. SSP Raw Interrupt Status register (RIS - address 0x4004 0018) bit description
This read-only register contains a 1 for each interrupt condition that is asserted and
enabled in the IMSC. When an SSP interrupt occurs, the interrupt service routine should
read this register to determine the cause(s) of the interrupt.
Table 213. SSP Masked Interrupt Status register (MIS -address 0x4004 001C) bit description
Software can write one or more one(s) to this write-only register, to clear the
corresponding interrupt condition(s) in the SSP controller. Note that the other two interrupt
conditions can be cleared by writing or reading the appropriate FIFO, or disabled by
clearing the corresponding bit in IMSC.
Bit
0
1
2
3
31:4
Bit
0
1
2
3
31:4
Symbol
RORRIS
RTRIS
RXRIS
TXRIS
-
Symbol
RORMIS
RTMIS
RXMIS
TXMIS
-
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Description
This bit is 1 if another frame was completely received while the
RxFIFO was full. The ARM spec implies that the preceding
frame data is overwritten by the new frame data when this
occurs.
This bit is 1 if the Rx FIFO is not empty, and has not been read
for a “time-out period”. The time-out period is the same for
master and slave modes and is determined by the SSP bit
rate: 32 bits at PCLK / (CPSDVSR × [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full.
This bit is 1 if the Tx FIFO is at least half empty.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Description
This bit is 1 if another frame was completely received while the
RxFIFO was full, and this interrupt is enabled.
This bit is 1 if the Rx FIFO is not empty, has not been read for
a “time-out period”, and this interrupt is enabled. The time-out
period is the same for master and slave modes and is
determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR
× [SCR+1]).
This bit is 1 if the Rx FIFO is at least half full, and this interrupt
is enabled.
This bit is 1 if the Tx FIFO is at least half empty, and this
interrupt is enabled.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
Rev. 1.1 — 10 March 2011
Chapter 12: LPC122x SSP controller
UM10441
© NXP B.V. 2011. All rights reserved.
Reset value
0
0
0
1
NA
Reset value
0
0
0
0
NA
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