OM13008,598 NXP Semiconductors, OM13008,598 Datasheet - Page 259

• Manufacturer Part Number: OM13008,598
• Description: BOARD LPC XPRESSO LPC122X
• Manufacturer: NXP Semiconductors
• Series: LPCXpressor

Specifications of OM13008,598

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-6642; OM13008

NXP Semiconductors
Table 241: Match Control Register (MCR, address 0x4001 8014 (CT32B0) and 0x4001 C014 (CT32B1)) bit description
UM10441
User manual
Bit
0
1
2
3
4
Symbol Value Description
MR0I
MR0R
MR0S
MR1I
MR1R
14.7.5 Prescale Counter Register
14.7.6 Match Control Register
1
0
1
0
1
0
1
0
1
0
Table 239: Prescale registers (PR, address 0x4001 800C (CT32B0) and 0x4001 C00C
The 32-bit Prescale Counter controls division of PCLK by some constant value before it is
applied to the Timer Counter. This allows control of the relationship between the resolution
of the timer and the maximum time before the timer overflows. The Prescale Counter is
incremented on every PCLK. When it reaches the value stored in the Prescale Register,
the Timer Counter is incremented, and the Prescale Counter is reset on the next PCLK.
This causes the TC to increment on every PCLK when PR = 0, every 2 PCLKs when
PR = 1, etc.
Table 240: Prescale registers (PC, address 0x4001 8010 (CT32B0) and 0x4001 C010
The Match Control Register is used to control what operations are performed when one of
the Match Registers matches the Timer Counter. The function of each of the bits is shown
in
Bit
31:0
Bit
31:0
Interrupt on MR0: an interrupt is generated when MR0 matches the value in the TC.
Enabled
Disabled
Reset on MR0: the TC will be reset if MR0 matches it.
Enabled
Disabled
Stop on MR0: the TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches
the TC.
Enabled
Disabled
Interrupt on MR1: an interrupt is generated when MR1 matches the value in the TC.
Enabled
Disabled
Reset on MR1: the TC will be reset if MR1 matches it.
Enabled
Disabled
Table
241.
Symbol
PCVAL
Symbol
PC
(CT32B1)) bit description
(CT32B1)) bit description
All information provided in this document is subject to legal disclaimers.
Rev. 1.1 — 10 March 2011
Description
Prescaler value.
Description
Prescale counter value.
Chapter 14: LPC122x 32-bit Counter/timer 0/1 (CT32B0/1)
UM10441
© NXP B.V. 2011. All rights reserved.
259 of 442
Reset
value
0
0
0
0
0
Reset
value
0
Reset
value
0